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Visitor jchou.1992
Visitor
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Registered: ‎01-01-2019

How can Ultrascal+100G Ethernet IP connect to AXI bus?

Hello:

 

 I'm using ZU17EG for my design. I used Vivado Block Gen to generate "Zynq" and" Ultrascale+100G Ethernet subsystem" in my design.

Then I run "Block & Connection Automation",  only rest & clock signals are connected. All data & control signals are floating. Not interconnection to Zynq. How can I connect them?  Which IP should I add?

 

BTW, Does Xilinx have reference design such as document, schematics, demo program regarding this?

 

Thanks

Jimmy 

 

 

 

 

 

 

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