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2,780 Views
Registered: ‎04-02-2017

How to use MII interface IP from Vivado IP catalog

Hi, 

 

I want to use MII interface from vivado 2016.4 --> IP Catalog --> interfaces --> Advanced --> mii v1.0

but how to get the license to use this IP?

can someone tell me the procedure to enable this IP? and any related wrapper code and doc?

I am using ARTY board for my design.

 

I want to use Ethernet data from RJ45 jack --> PHY chip--> FPGA (data processing)

As of now I am trying for 10/100 M speed.

 

Please let me know how can I enable this mii interface IP and utilize in my design. and if any related reference design pls share.

 

Thank you

Silpa Pagadala.

 

 

 

 

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7 Replies
Xilinx Employee
Xilinx Employee
2,768 Views
Registered: ‎02-06-2013

Re: How to use MII interface IP from Vivado IP catalog

Hi

 

You can directly use the Ethernet lite core which supports MII interface and no need to use extra shim core.

 

https://www.xilinx.com/support/documentation/ip_documentation/axi_ethernetlite/v3_0/pg135-axi-ethernetlite.pdf

Regards,

Satish

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Moderator
Moderator
2,749 Views
Registered: ‎08-25-2009

Re: How to use MII interface IP from Vivado IP catalog

Do you mean you would like to use the pre-defined MII interface in your custom IP?

You can do this in IP Packager by auto inferring the MII interface shown as below: Capture.JPG

 

More details can be found in UG1118:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_1/ug1118-vivado-creating-packaging-custom-ip.pdf

 

Hope this helps!

"Don't forget to reply, kudo and accept as solution."
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2,746 Views
Registered: ‎04-02-2017

Re: How to use MII interface IP from Vivado IP catalog

Thanks for the update Nanz,

 

Is this option is available for custom IP only?

I could not find the mentioned window in vivado directly.

 

PHY chip(DP83848JSQ/NOPB) is available on board. I want to interface it with FPGA (ARTIX 7 in ARTY board).

 

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Xilinx Employee
Xilinx Employee
2,741 Views
Registered: ‎02-06-2013

Re: How to use MII interface IP from Vivado IP catalog

Hi Silpa,

 

As mentioned in my previous mode you can directly use the Axi Ethernet Lite core or temac in MII mode to interface with your PHY chip(DP83848JSQ/NOPB)  available on your board and no need to use the MII to RMII core.

 

Don't you need a MAC to interface with the PHY or what is your specific application/Constraint that need the MII to RMII shim instead of direct MAC core with MII interface 

Regards,

Satish

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2,681 Views
Registered: ‎04-02-2017

Re: How to use MII interface IP from Vivado IP catalog

Thank you for response Satish.

Am new to AXI, is there any reference design for the above mentioned one?

 

Thanks & Regards,

Silpa 

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2,677 Views
Registered: ‎04-02-2017

Re: How to use MII interface IP from Vivado IP catalog

Since I am not using any processor in my design. 

 

It is only FPGA Design. 

Requirement is PHY --> FPGA interface using MII.

 

 

 

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Scholar dpaul24
Scholar
2,670 Views
Registered: ‎08-07-2014

Re: How to use MII interface IP from Vivado IP catalog

No matter what you do you must use a MAC core to analyze data received via RJ45.

 

<1>

If you wish to use the TEMAC (hardware evaluation license is free; the bit/stream will run for a hour or two) core just generate the TEMAC IP core with MII mode.

After it is done, in Vivado, if you right click on the core, Xilinx gives you an option to generate an example_design for the TEMAC core with MII i/f (it will be created as a separate project).

 

If you study this example_design CAREFULLY, you will understand how a design with MAC core having MII i/f works.

 

<2>

I never used the Axi Ethernet Lite coreso will not comment about it.

 

Since I am not using any processor in my design.

It is not needed!

 

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