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Observer aobeid
Observer
8,398 Views
Registered: ‎09-25-2012

IBERT / Virtex-5 / Invalid line rate & REFCLK

Hi all,

 

I'm facing a problem when using IBERT on XC5VFX70T-2-FF665.

The line rate, after programming the FPGA, doesn't match the selected one using the wizard in Core Generator.

Furthermore, the *.xco file includes the following statements that don't match as well:

  • CSET x0y2_gtx_dual_rx_line_rate=3.125
  • CSET x0y2_gtx_dual_rx_refclk_val=156.25

 

In what follows, snapshots are given that illustrates the IBERT settings:

IBERT_CoreGen_1.jpg

 

IBERT_CoreGen_2.jpg

 

IBERT_CoreGen_3.jpg

 

IBERT_CoreGen_4.jpg

 

IBERT_CoreGen_5.jpg

 

Moreover, when selecting Near-End PCS the line rate reaches 7.812 Gbps which exceeds the limit of 6.5.

 

Thanks in advance for any feedback.

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4 Replies
Moderator
Moderator
8,382 Views
Registered: ‎02-16-2010

Re: IBERT / Virtex-5 / Invalid line rate & REFCLK

Which version of ISE tool you are using?

can you check the following attributes in IBERT GUI?
PLL_DIVSEL_FB
PLL_DIVSEL_REF
DIV

I am referring to the Equation 5-1 in ug198. By using the equation you should be able to find the expected line rate.

f(PLL Clock) calculated from this equation is half of the line rate.

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Observer aobeid
Observer
8,380 Views
Registered: ‎09-25-2012

Re: IBERT / Virtex-5 / Invalid line rate & REFCLK

 

Thanks very much for your reply.

 

Which version of ISE tool you are using?

  • Version 14.7


can you check the following attributes in IBERT GUI?

  • PLL_DIVSEL_FB = 5 (Radix: UCF)
  • PLL_DIVSEL_REF = 2 (Radix: UCF)
  • DIV = 4 since OVERSAMPLE_MODE = 0 (Radix: Bin) & INTDATAWIDTH = 0 (Radix: Bin)


According to equation 5-1, f(PLL Clock) = 2.5 Ghz => Line rate should be 5 Gbps.

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Moderator
Moderator
8,376 Views
Registered: ‎02-16-2010

Re: IBERT / Virtex-5 / Invalid line rate & REFCLK

To be accurate, can you check the attributes on hardware when you load IBERT bit stream. That could confirm if the observations are related to some tool issue.
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Observer aobeid
Observer
8,371 Views
Registered: ‎09-25-2012

Re: IBERT / Virtex-5 / Invalid line rate & REFCLK

The values are taken directly from ChipScope after loading the bit stream.

 

IBERT_ChipScope_PLL_DRPSettings.jpg

 

 

IBERT_ChipScope_PLL_PortSettings.jpg

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