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Participant andrewcb
Participant
495 Views
Registered: ‎07-03-2008

JESD GTHE4 TxOutClk frequency error

Hi,

 

I am using the Xilinx JESD_PHY IP block in a ZCU102 (xczu9eg) design.

 

I set my Line rate to 3Gbps and was expecting TXOUTCLK to be 3e9/40 = 75MHz, but when I look at the IP pin parameters the clock is set to 75001875.047. Other line rates 1,2,4 & 5 work OK, but 3 does not :0(

 

Has anyone seen this before?

 

It's easy to try, create a ZCU102 example in Vivado (2017.4), add the JESD_PHY IP and set the line rate to 3Gbps. ClickOK and check the TXOUTCLK pin frequency.

 

Regards

Andrew

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Moderator
Moderator
453 Views
Registered: ‎02-16-2010

Re: JESD GTHE4 TxOutClk frequency error

Thanks for reporting this issue. I find that this issue seems identified and fixed already. I do not find it exists with next release of the Vivado tool.
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