04-15-2019 09:03 AM
I'm working with the ZC706 and the JESD Tx, with the core separated from the phy, so I need two clocks: refclk and core_clk.
- Core_clk is serial lane rate / 40 = 250MHz.
- Refclk is 125MHz or 250MHz (I tried with both of them).
Both come from the same source. Refclk goes to IBUFDS_GTE2, the output of the buffer is routed to the QPLL and also to the PL via a BUFG (I tried it and it works). The output of the BUFG goes to a PLL/MMCM and then to the core_clk.
My receiver is able to sync and I even see data, but there are a lot of interruptions. After probing a lot of signals, I can tell you that my clocks are all ok (right frequency and right waveform), the input reset of JESD core is always 0 (no reset), tx_reset_gt is always low (no reset), output reset of JESD PHY toggles, sync toggles and qpll_lock_out toggles.
I realized QPLL lost of lock makes the lost of sync and then the output reset of JESD PHY toggles.
It is the same behaviour in subclass 0 and subclass 1.
How could the QPLL unlock so often?
Am I doing something wrong?
Please help me find out a solution.
Thanks in advance
04-16-2019 12:31 AM
Thanks for your reply.
I'm sorry, I have no idea how to do so. The IBERT is not integrated in the JESD IP and the one I found in the IP catalog is bound to the GTX transceiver. If I use that IP, I must delete the JESD IP so the design will be different and that won't help me.
I tried to follow AR 60024 but I don't find drp ports on the JESD IP.
04-16-2019 01:01 AM
The eye is to do with the mechanics of the baord, not the actual IP,
so you could swap in an eye monitor,
If you don't have a good eye, then all bets are off.
I recently bumped into this,
chapter 6 is interesting,
04-16-2019 08:02 AM - edited 04-16-2019 08:03 AM
I don't understand. How could I see the eye diagram with IBERT since it is in the FPGA?
The IBERT will just 'probe' signals inside the FPGA, which should have no problem, while I would like to see the signal near the receiver.
I still have no idea of why the link is lost and/or the QPLL unlocks..
04-16-2019 10:03 AM