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Registered: ‎10-11-2017

JESD204B core clock

Hello everyone!

I am using JESD204B(subclass 1) IP core as a receiver(shared logic in core)

I found that when I set  the Lane rate with 4.9152Gbps,in this case the JESD204B reference clock and core clock are both 122.88MHz.That means  I  only need reference clock. I found in this case the JESD204B can alway run right.

However when the Lane rate is 1.2288Gbps,the JESD204B reference clock is 122.88MHz and the core clock is 30.72MHz.In this case I need both clocks.However the IP core can not  dessert sync signal.

So I guess there may be something wrong with the core clock.

My core clock  and reference clock are both from the clock distribution chip.The reference clock connect to the pin MGTREFCLK.The core clock connect to the pin MRCC  (HR IO bank) . Is this right?

What constraints should I add for the core clock?

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Xilinx Employee
Xilinx Employee
Registered: ‎10-19-2011

Re: JESD204B core clock

Hi @kristen123,


connecting to MRCC should be okay (I assume you have a 7 series setup). You would need to give at least correct location and IO_STANDARD constraints for it to work properly.

If you did this already you might need to check first that the clocks are seen inside the FPGA by bringing them out again and measure them.

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