We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Showing results for 
Search instead for 
Did you mean: 
Visitor apiskur
Registered: ‎01-16-2019

LWIP UDP Communications Not Working on ZCU-102 A53 Cores 2 and 3


I was wondering if anyone has run into this particular problem, or could possibly help me find a solution.  I am developing a baremetal application for a ZCU-102 that communicates with another application running on a PC.  I have been partially successful in using the LWIP raw UDP functionality of the Xilinx SDK's board support package.  The application I have developed communicates just fine if I load it into cores 0 or 1 of the A53 processor in the ZynqMP on the eval board.  If I take the exact same application and load it onto cores 2 or 3 of the A53 processor, it ceases to be able to communicate via UDP.  Activating debug statements in the LWIP, via the BSP, produces no useful information. 

As a sanity check, I loaded the UDP perf client example program from the SDK onto my ZCU-102, on A53 core 2 and ran the server component on my PC.  The UDP perf client will not initiate the conversation when running on core 2 or core 3.  It works a lot better on core 0 or core 1. 

Has anyone experienced this before?  I am using the Xilinx SDK version 2018.2.  I am using the default example FSBL and default ZCU-102 hardware profile.  Whether I program QSPI or load via jtag makes no difference.  




Tags (3)
0 Kudos