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Newbie panchamayu
Newbie
2,694 Views
Registered: ‎05-11-2017

Monitoring RGMII from AXI 1G/2.5G Ethernet Subsystem v7.0

I am in need of some help with monitoring RGMII wires coming out of a AXI 1G/2.5G Ethernet Subsystem v7.0 IP block. Essentially the design has been tested and I can send data through the ethernet IP, but now I want to "monitor" the RGMII lines coming from the IP block.

 

I have created an IP which takes in two RGMII busses, but involves the rgmii_txc and rgmii_tx_ctl lines, which are logic lines generated by the IP itself. This makes the AXI IP produces Ouput Buffers on the outputs, meaning they cannot be routed to other IP in the block system, and should be going to a top level port (a external pin on the FPGA). I find I can route the rgmii_tx_ctl internally without any errors, but if I try to route the rgmii_txc line, then some OBUF errors occur. (rgmii_tx_ctl_obuf_i pin O drives one or more invalid loads. The loads are: zedboard_axieth_i/rgmii_detector_0/U0/detect_out/active_reg )

 

Attached is the block I am trying to use.

 

Thanks

 

 

 

Screenshot from 2017-07-18 20-15-22.png
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6 Replies
Scholar dpaul24
Scholar
2,661 Views
Registered: ‎08-07-2014

Re: Monitoring RGMII from AXI 1G/2.5G Ethernet Subsystem v7.0

 

What exactly are you trying to monitor? Toggle some o/p's when rgmii_tx_ctl or rgmii_rx_ctl transitions?

Can't this rx/tx rgmii monitoring be done at the PHY chip level (some signals or LEDs blinking or something like that)?

 

Remember that rgmii_tx_* signals are generated from ODDR outputs, so these signals MAY NOT be as flexible (to use) compared to other signals. Similarly rgmii_rx_* (other than the clk) should first go to IDDRs after passing out of the input buffers.

 

Also remember that the txc and rxc must be treated as async clks.

 

I have worked with TEMACs and in all cases there xilinx never puts any type of logic between IDDRs/ODDRs and ip/op buffers.

I may be wrong, so I am just guessing the design approach!

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Newbie panchamayu
Newbie
2,561 Views
Registered: ‎05-11-2017

Re: Monitoring RGMII from AXI 1G/2.5G Ethernet Subsystem v7.0


@dpaul24 wrote:

 

What exactly are you trying to monitor? Toggle some o/p's when rgmii_tx_ctl or rgmii_rx_ctl transitions?

Can't this rx/tx rgmii monitoring be done at the PHY chip level (some signals or LEDs blinking or something like that)?

 

Remember that rgmii_tx_* signals are generated from ODDR outputs, so these signals MAY NOT be as flexible (to use) compared to other signals. Similarly rgmii_rx_* (other than the clk) should first go to IDDRs after passing out of the input buffers.

 

Also remember that the txc and rxc must be treated as async clks.

 

I have worked with TEMACs and in all cases there xilinx never puts any type of logic between IDDRs/ODDRs and ip/op buffers.

I may be wrong, so I am just guessing the design approach!


 Thanks for the reply!

 

I am trying to monitor the txc and tx_ctl lines for a transition (In the RGMII spec, tx_ctl is a DDR line, and on the rising edge of txc, it will be asserted on whether there is some data to be transmitted from the MAC to the PHY) I am looking to create a interrupt/signal of some sort as soon as the MAC begins to transmit data to the PHY. 

 

Can this monitoring be done elsewhere? Not too sure, there could be a better way (Maybe monitoring the AXI lines to the AXI 1G/2.5G Ethernet IP), but I just need to monitor when one ethernet PHY begins transmitting and monitor another one for when it receives the transmission. I could also just write my own MAC instead.

 

Yea that whole ODDR outputs is what is stopping me at the Implementation stage. I get errors from Vivado saying that its not a top level port. I did not know about the IDDRs, which is why I was thinking if there was a way I could add the buffers myself. If I could add the buffers, I could have my IP be like a man-in-the-middle for all communication between the PHY and MAC.

 

Do you think that might be a way to solve the problem I am havaing?

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Scholar dpaul24
Scholar
2,543 Views
Registered: ‎08-07-2014

Re: Monitoring RGMII from AXI 1G/2.5G Ethernet Subsystem v7.0

Do you think that might be a way to solve the problem I am havaing?

 

In which mode did you generate the MAC IP? RGMII I guess!

In that case very little can be done.

 

Writing your own MAC would involve lot of time and effort (although there is a free version on the GitHub from someone's master-thesis, I don't know how well it performs).

 

If possible, generate the MAC core in GMII mode. Then use the Xilinx IP gmii-to-rgmii. Finally try to put your monitor block on the GMII interface. The gmii_*_dv/en would tell your when tx/rx is taking place.

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FPGA enthusiast!
All PMs will be ignored
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Newbie panchamayu
Newbie
2,530 Views
Registered: ‎05-11-2017

Re: Monitoring RGMII from AXI 1G/2.5G Ethernet Subsystem v7.0


@dpaul24 wrote:

Do you think that might be a way to solve the problem I am havaing?

 

In which mode did you generate the MAC IP? RGMII I guess!

In that case very little can be done.

 

Writing your own MAC would involve lot of time and effort (although there is a free version on the GitHub from someone's master-thesis, I don't know how well it performs).

 

If possible, generate the MAC core in GMII mode. Then use the Xilinx IP gmii-to-rgmii. Finally try to put your monitor block on the GMII interface. The gmii_*_dv/en would tell your when tx/rx is taking place.


Yes indeed, sorry for not being clear about it, but yes this is with RGMII.

 

Oh true, that last idea actually seems worthwhile investigating! GMII is easier to know when it is transmitting thanks to not being DDR. 

 

I was going to try to see what was inside the GMII to RGMII block, to see if I could modify it and then package it up as a new IP. But I found that the code was encrypted when I tried to view it. 

 

I have made code for a packet generator, which I could use as the MAC, and produce the packets I want (I just need traffic, i dont care what information is in the traffic). I am working on implementing this way, but I shall look into the RGMII/GMII shim way if this doesnt work.

 

Thanks for the help, its nice to have another point of view on my problem!

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Scholar dpaul24
Scholar
2,516 Views
Registered: ‎08-07-2014

Re: Monitoring RGMII from AXI 1G/2.5G Ethernet Subsystem v7.0

You are welcome!

 

Again I don't know which version of Vivado or which Xilinx part number you are using.

 

But I also had a problem with generating the latest version of the Xil gmii2rgmii IP for the Artix7 device.

So I used on older version (pg160-gmii-to-rgmii_v2.0.pdf) of the RTL and modified it as per my requirements.All you need is to play around various clock buffers, IDDRs/ODDRs, IDELAY2 and the constraints file.

 

See if it can be downloaded from somewhere.  Else I can send you a zip containing all of the related codes via a PM if you want.

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FPGA enthusiast!
All PMs will be ignored
--------------------------------------------------------------------------------------------------------
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Newbie panchamayu
Newbie
2,473 Views
Registered: ‎05-11-2017

Re: Monitoring RGMII from AXI 1G/2.5G Ethernet Subsystem v7.0

I am using Vivado 2017.2, and I am developing on the Zedboard with an Ethernet FMC card (http://ethernetfmc.com/).

 

I found a way, but making a packet generator for the RGMII bus (for both ends), and the creating output signals when it recieves/sends a packet. This way I dont need to use IP from Xilinx and I can monitor the pins out.

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