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Observer wjun
Observer
9,017 Views
Registered: ‎02-11-2013

More clocks in the clock region than the maximum number of clocks

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Hello,

 

I'm trying to use four 64b66b aurora cores on a single quad, each using one lane, separately.

They all run with the same refclock, at the same bandwidth, using the gtxe common.

This works fine with two cores (I haven't tried three), but four fails with

 

ERROR: [Place 30-177] Unroutable Placement! There are more clocks in the clock region than the maximum number of allowed clocks per clock region.

ERROR: CLOCKREGION_X1Y6 has 13 clocks. The maximum number of clocks allowed in any clock region is 12.

 

Each core uses three clocks, (user clock, rx clock, sync clock), and I have a bufg for the 50MHz init clock, which adds up to 13.

 

What would be the best way to solve this?

(1) Is it possible to use the USER_CLOCK from one core for the other cores as well?

(2) The transceiver user guide says I can clock other cores using the tx out clock of one core. Is that the suggested method with separate cores running separately, as well?

 

Thanks!

 

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Explorer
Explorer
16,331 Views
Registered: ‎08-19-2014

Re: More clocks in the clock region than the maximum number of clocks

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Having worked with the 64b66b core with Virtex 6, I recall there was the user clock, the shim clock, and the sync clock.  I'm not sure if the 4th clock is the actual MGT clock in your case.  Anyway, if all your independent lanes are running at the same data rate, then you can use one DCM to generate the user, sync, and shim clocks for your design.  When you generate the Aurora 64b66b core, each generated core has its own DCM which is redundant in your design scenario.  You'll have to do some modifications to the generated code, but it shouldn't be much.

 

-Jordan

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2 Replies
Explorer
Explorer
16,332 Views
Registered: ‎08-19-2014

Re: More clocks in the clock region than the maximum number of clocks

Jump to solution

Having worked with the 64b66b core with Virtex 6, I recall there was the user clock, the shim clock, and the sync clock.  I'm not sure if the 4th clock is the actual MGT clock in your case.  Anyway, if all your independent lanes are running at the same data rate, then you can use one DCM to generate the user, sync, and shim clocks for your design.  When you generate the Aurora 64b66b core, each generated core has its own DCM which is redundant in your design scenario.  You'll have to do some modifications to the generated code, but it shouldn't be much.

 

-Jordan

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Observer wjun
Observer
8,987 Views
Registered: ‎02-11-2013

Re: More clocks in the clock region than the maximum number of clocks

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Thanks! It seems to work!

 

I used one MMCM clocked from the tx_out_clk of one core,

and used its output as USER_CLK and SYNC_CLK of all four cores.

It seems to work correctly.

 

:)

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