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8,403 Views
Registered: ‎06-01-2010

Multiple SGMII Ethernet PHYs at ML507

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I need three Gigabit Ethernet-Ports at a ML507 board, and I would like to use SGMII interfaces from the FPGA to the PHYs. The first PHY could be the onboard Marvell-chip, which works without problems. I added an additional xps_ll_temac ("Hard_Ethernet_MAC2") for the two additional MACs, and tried to connect them to the SFP and the SMA-connectors.

 

I tried the following constraints:

 

########### Hard_Ethernet_MAC ##########################################

Net Hard_Ethernet_MAC_MGTCLK_P_pin LOC=P4 |  IOSTANDARD = DIFF_LVCMOS25;

Net Hard_Ethernet_MAC_MGTCLK_N_pin LOC=P3 |  IOSTANDARD = DIFF_LVCMOS25;

Net fpga_0_Hard_Ethernet_MAC_TemacPhy_RST_n_pin LOC=J14  |  IOSTANDARD = LVCMOS25  |  TIG;

Net fpga_0_Hard_Ethernet_MAC_PHY_MII_INT_pin LOC=H20  |  IOSTANDARD = LVCMOS25  |  TIG;

# Marvell

Net fpga_0_Hard_Ethernet_MAC_MDC_0_pin LOC=H19  |  IOSTANDARD = LVCMOS25;

Net fpga_0_Hard_Ethernet_MAC_MDIO_0_pin LOC=H13  |  IOSTANDARD = LVCMOS25;

Net Hard_Ethernet_MAC_TXP_0_pin LOC=M2 |  IOSTANDARD = DIFF_LVCMOS25;

Net Hard_Ethernet_MAC_TXN_0_pin LOC=N2 |  IOSTANDARD = DIFF_LVCMOS25;

Net Hard_Ethernet_MAC_RXP_0_pin LOC=N1 |  IOSTANDARD = DIFF_LVCMOS25;

Net Hard_Ethernet_MAC_RXN_0_pin LOC=P1 |  IOSTANDARD = DIFF_LVCMOS25;

 

########### Hard_Ethernet_MAC2 ##########################################

Net Hard_Ethernet_MAC2_MGTCLK_P_pin LOC=H4 |  IOSTANDARD = DIFF_LVCMOS25;

Net Hard_Ethernet_MAC2_MGTCLK_N_pin LOC=H3 |  IOSTANDARD = DIFF_LVCMOS25;

#SFP:

Net Hard_Ethernet_MAC2_MDC_0_pin LOC=R26  |  IOSTANDARD = LVCMOS18;

Net Hard_Ethernet_MAC2_MDIO_0 LOC=U28  |  IOSTANDARD = LVCMOS18;

Net Hard_Ethernet_MAC2_TXP_0_pin LOC=F2 |  IOSTANDARD = DIFF_LVCMOS25;

Net Hard_Ethernet_MAC2_TXN_0_pin LOC=G2 |  IOSTANDARD = DIFF_LVCMOS25;

Net Hard_Ethernet_MAC2_RXP_0_pin LOC=G1 |  IOSTANDARD = DIFF_LVCMOS25;

Net Hard_Ethernet_MAC2_RXN_0_pin LOC=H1 |  IOSTANDARD = DIFF_LVCMOS25;

#SMA (MGT):

Net Hard_Ethernet_MAC2_TXP_1_pin LOC=L2 |  IOSTANDARD = DIFF_LVCMOS25;

Net Hard_Ethernet_MAC2_TXN_1_pin LOC=K2 |  IOSTANDARD = DIFF_LVCMOS25;

Net Hard_Ethernet_MAC2_RXP_1_pin LOC=K1 |  IOSTANDARD = DIFF_LVCMOS25;

Net Hard_Ethernet_MAC2_RXN_1_pin LOC=J1 |  IOSTANDARD = DIFF_LVCMOS25;

 

 

With XPS 11.4 I was able to generate a working bitstream already (although I could not really test the second/third ethernet ports because of a lack of PHYs & magnetics). Since I updated to XPS 12.1 I get the following error message (repeated for each RX and TX signal of the second and third port -> eight times):

Place:990 - Unroutable Placement! A GT / OPAD component pair have been found that are not placed at a routable GT
   / OPAD site pair. The GT component
   <Hard_Ethernet_MAC2/Hard_Ethernet_MAC2/V5HARD_SYS.I_TEMAC/DUAL_SGMII_FX.I_EMAC_TOP/GTX_DUAL_1000X_inst/GTX_1000X/tile
   0_rocketio_wrapper_gtx_i/gtx_dual_i> is placed at site <GTX_DUAL_X0Y3>. The corresponding OPAD component
   <Hard_Ethernet_MAC2_TXN_0_pin> is placed at site <OPAD_X0Y20>. The GT <TXN0> pin can route to the OPAD only if the
   load component is placed at an offset of (3, -1) with respect to the driver component. This placement is UNROUTABLE
   in PAR and therefore, this error condition should be fixed in your design. You may use the CLOCK_DEDICATED_ROUTE
   constraint in the .ucf file to demote this message to a WARNING in order to generate an NCD file. This NCD file can
   then be used in FPGA Editor to debug the problem. A list of all the COMP.PINS used in this clock placement rule is
   listed below. These examples can be used directly in the .ucf file to demote this ERROR to a WARNING.
   < PIN
   "Hard_Ethernet_MAC2/Hard_Ethernet_MAC2/V5HARD_SYS.I_TEMAC/DUAL_SGMII_FX.I_EMAC_TOP/GTX_DUAL_1000X_inst/GTX_1000X/tile
   0_rocketio_wrapper_gtx_i/gtx_dual_i.TXN0" CLOCK_DEDICATED_ROUTE = FALSE; >
   < PIN "Hard_Ethernet_MAC2_TXN_0_pin_OBUF.I" CLOCK_DEDICATED_ROUTE = FALSE; >

 

ERROR:Place:990 - Unroutable Placement! A GT / OPAD component pair have been found that are not placed at a routable GT

   / OPAD site pair. The GT component

   <Hard_Ethernet_MAC2/Hard_Ethernet_MAC2/V5HARD_SYS.I_TEMAC/DUAL_SGMII_FX.I_EMAC_TOP/GTX_DUAL_1000X_inst/GTX_1000X/tile

   0_rocketio_wrapper_gtx_i/gtx_dual_i> is placed at site <GTX_DUAL_X0Y2>. The corresponding OPAD component

   <Hard_Ethernet_MAC2_TXN_0_pin> is placed at site <OPAD_X0Y20>. The GT <TXN0> pin can route to the OPAD only if the

   load component is placed at an offset of (3, -1) with respect to the driver component. This placement is UNROUTABLE

   in PAR and therefore, this error condition should be fixed in your design. You may use the CLOCK_DEDICATED_ROUTE

   constraint in the .ucf file to demote this message to a WARNING in order to generate an NCD file. This NCD file can

   then be used in FPGA Editor to debug the problem. A list of all the COMP.PINS used in this clock placement rule is

   listed below. These examples can be used directly in the .ucf file to demote this ERROR to a WARNING.

   < PIN

   "Hard_Ethernet_MAC2/Hard_Ethernet_MAC2/V5HARD_SYS.I_TEMAC/DUAL_SGMII_FX.I_EMAC_TOP/GTX_DUAL_1000X_inst/GTX_1000X/tile

   0_rocketio_wrapper_gtx_i/gtx_dual_i.TXN0" CLOCK_DEDICATED_ROUTE = FALSE; >

   < PIN "Hard_Ethernet_MAC2_TXN_0_pin_OBUF.I" CLOCK_DEDICATED_ROUTE = FALSE; >

 

 

 

 

 

If I comment the net constraints for  "Hard_Ethernet_MAC2_MDC_0_pin" and "Hard_Ethernet_MAC2_MDIO_0" the error does not occur. It seems like the MDC and MDIO wires influence the placement of the MACs, GTX or pins. The pins are defined by the ML507 board layout and cannot be changed.

What is wrong or what is missing?

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1 Solution

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Highlighted
Explorer
Explorer
8,837 Views
Registered: ‎10-01-2008

Re: Multiple SGMII Ethernet PHYs at ML507

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Hi,

 

Regarding your problem, please follow our GTP User Guide (UG196) to add the constraints.
http://www.xilinx.com/support/documentation/user_guides/ug196.pdf
 
According to it, you just need to add GTP Locations and REFCLK pins locations constraints.
You don’t need to add GTP pins locations constraints. Would this work if you remove them in your UCF?

 

BR,

Yan Shun Li

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8 Replies
8,129 Views
Registered: ‎08-03-2010

Re: Multiple SGMII Ethernet PHYs at ML507

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I have a similar issue, my MDIO/MDC pin assignment changes and I am getting the same error, can anyone shed some light on this?

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Highlighted
Explorer
Explorer
8,838 Views
Registered: ‎10-01-2008

Re: Multiple SGMII Ethernet PHYs at ML507

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Hi,

 

Regarding your problem, please follow our GTP User Guide (UG196) to add the constraints.
http://www.xilinx.com/support/documentation/user_guides/ug196.pdf
 
According to it, you just need to add GTP Locations and REFCLK pins locations constraints.
You don’t need to add GTP pins locations constraints. Would this work if you remove them in your UCF?

 

BR,

Yan Shun Li

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Explorer
Explorer
8,051 Views
Registered: ‎10-01-2008

Re: Multiple SGMII Ethernet PHYs at ML507

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Any example of GTX placement constraints is as follows.

 

 

;
; Instantiate the GTX_DUAL tiles in locations X0Y7 to X0Y1
;
INST design_root/gtx_dual[1]/gtx_dual LOC=GTX_DUAL_X0Y1;
INST design_root/gtx_dual[2]/gtx_dual LOC=GTX_DUAL_X0Y2;
INST design_root/gtx_dual[3]/gtx_dual LOC=GTX_DUAL_X0Y3;
INST design_root/gtx_dual[4]/gtx_dual LOC=GTX_DUAL_X0Y4;
INST design_root/gtx_dual[5]/gtx_dual LOC=GTX_DUAL_X0Y5;
INST design_root/gtx_dual[6]/gtx_dual LOC=GTX_DUAL_X0Y6;
INST design_root/gtx_dual[7]/gtx_dual LOC=GTX_DUAL_X0Y7;
;
; Connect the REFCLK_PAD_(N/P) differential pair to the middle
; GTX_DUAL tile (GTX_DUAL_X0Y4)
;
NET refclk_pad_n LOC=P3;
NET refclk_pad_p LOC=P4;

 

 

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8,047 Views
Registered: ‎06-01-2010

Re: Multiple SGMII Ethernet PHYs at ML507

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It works with the location constraints, thank you very much for your assistance.

 

For your interest, a bug in XPS was another reason why the second TEMAC did not function (CR 567651):

The port setting for Llink_Temac1_Clk was not shown in the GUI unless I have added it manually in the system.mhs file.

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Observer gi4you
Observer
7,981 Views
Registered: ‎09-24-2009

Re: Multiple SGMII Ethernet PHYs at ML507

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Hello,

 

Anybody has example mhs and ucf file for dual SGMII on ML507 ?

 

Thank you,

Kiman

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7,959 Views
Registered: ‎06-01-2010

Re: Multiple SGMII Ethernet PHYs at ML507

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I am sorry, I don't have a working project with dual SGMII anymore, because I am using RGMII now (because of other reasons).

But I found some files of a faulty project (3x SGMII) in a old email.

- Marvell PHY on ML507 connected to "Hard_Ethernet_MAC"

- SFP-slot and SMA-connectors connected to dual "Hard_Ethernet_MAC2"

 

I remember the following "stumbling blocks" (to be checked):

- The physical interface for the SFP module must be 1000BaseX instead of SGMII (will also influence the location constraints!).

- The port setting "Llink_Temac0_CLK" of Hard_Ethernet_MAC2 was not shown in the graphical user interface of XPS and had to be added manually in the MHS file.

 

I am not able to spend more time on this, maybe these examples of location constraints give you a hint...

 

Best Regards!

 

 

 

 

UCF-File:

 

########### Hard_Ethernet_MAC ##########################################

## Location constraints

INST "Hard_Ethernet_MAC/Hard_Ethernet_MAC/V5HARD_SYS.I_TEMAC/SINGLE_SGMII_FX.I_EMAC_TOP/GTX_DUAL_1000X_inst/GTX_1000X/tile0_rocketio_wrapper_gtx_i/gtx_dual_i" LOC = "GTX_DUAL_X0Y4";

INST "Hard_Ethernet_MAC/Hard_Ethernet_MAC/V5HARD_SYS.I_TEMAC/SINGLE_SGMII_FX.I_EMAC_TOP/v5_emac_wrapper/v5_emac" LOC = "TEMAC_X0Y0";

## Clock

Net Hard_Ethernet_MAC_MGTCLK_P_pin LOC=P4 |  IOSTANDARD = DIFF_LVCMOS25;

Net Hard_Ethernet_MAC_MGTCLK_N_pin LOC=P3 |  IOSTANDARD = DIFF_LVCMOS25;

Net Hard_Ethernet_MAC_TemacPhy_RST_n_pin LOC=J14  |  IOSTANDARD = LVCMOS25  |  TIG;

# Marvell PHY on ML507

Net Hard_Ethernet_MAC_MDC_0_pin LOC=H19  |  IOSTANDARD = LVCMOS25;

Net Hard_Ethernet_MAC_MDIO_0_pin LOC=H13  |  IOSTANDARD = LVCMOS25;

Net Hard_Ethernet_MAC_TXP_0_pin LOC=M2 |  IOSTANDARD = DIFF_LVCMOS25;

Net Hard_Ethernet_MAC_TXN_0_pin LOC=N2 |  IOSTANDARD = DIFF_LVCMOS25;

Net Hard_Ethernet_MAC_RXP_0_pin LOC=N1 |  IOSTANDARD = DIFF_LVCMOS25;

Net Hard_Ethernet_MAC_RXN_0_pin LOC=P1 |  IOSTANDARD = DIFF_LVCMOS25;

 

########### Hard_Ethernet_MAC2 ##########################################

## Location constraints

INST "Hard_Ethernet_MAC2/Hard_Ethernet_MAC2/V5HARD_SYS.I_TEMAC/DUAL_SGMII_FX.I_EMAC_TOP/GTX_DUAL_1000X_inst/GTX_1000X/tile0_rocketio_wrapper_gtx_i/gtx_dual_i" LOC = "GTX_DUAL_X0Y5";

INST "Hard_Ethernet_MAC2/Hard_Ethernet_MAC2/V5HARD_SYS.I_TEMAC/DUAL_SGMII_FX.I_EMAC_TOP/v5_emac_wrapper/v5_emac" LOC = "TEMAC_X0Y1";

## Clock

Net Hard_Ethernet_MAC2_MGTCLK_P_pin LOC=H4 |  IOSTANDARD = DIFF_LVCMOS25;

Net Hard_Ethernet_MAC2_MGTCLK_N_pin LOC=H3 |  IOSTANDARD = DIFF_LVCMOS25;

#SFP on ML507:

#Net Hard_Ethernet_MAC2_MDC_0_pin LOC=R26  |  IOSTANDARD = LVCMOS18; # too slow because of level shifting transistors

#Net Hard_Ethernet_MAC2_MDIO_0_pin LOC=U28  |  IOSTANDARD = LVCMOS18; # too slow because of level shifting transistors

Net Hard_Ethernet_MAC2_MDC_0_pin LOC=AN33  |  IOSTANDARD = LVCMOS25; # using HDR1_64 for tests

Net Hard_Ethernet_MAC2_MDIO_0_pin LOC=AN34  |  IOSTANDARD = LVCMOS25; # using HDR1_62 for tests

Net Hard_Ethernet_MAC2_TXP_0_pin LOC=F2 |  IOSTANDARD = DIFF_LVCMOS25;

Net Hard_Ethernet_MAC2_TXN_0_pin LOC=G2 |  IOSTANDARD = DIFF_LVCMOS25;

Net Hard_Ethernet_MAC2_RXP_0_pin LOC=G1 |  IOSTANDARD = DIFF_LVCMOS25;

Net Hard_Ethernet_MAC2_RXN_0_pin LOC=H1 |  IOSTANDARD = DIFF_LVCMOS25;

#SMA connectors (MGT) on ML507:

Net Hard_Ethernet_MAC2_TXP_1_pin LOC=L2 |  IOSTANDARD = DIFF_LVCMOS25;

Net Hard_Ethernet_MAC2_TXN_1_pin LOC=K2 |  IOSTANDARD = DIFF_LVCMOS25;

Net Hard_Ethernet_MAC2_RXP_1_pin LOC=K1 |  IOSTANDARD = DIFF_LVCMOS25;

Net Hard_Ethernet_MAC2_RXN_1_pin LOC=J1 |  IOSTANDARD = DIFF_LVCMOS25;

 

 

MHS-File:

 

 

BEGIN xps_ll_temac

 PARAMETER INSTANCE = Hard_Ethernet_MAC

 PARAMETER C_NUM_IDELAYCTRL = 2

 PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X0Y4-IDELAYCTRL_X1Y5

 PARAMETER C_PHY_TYPE = 4

 PARAMETER C_TEMAC1_ENABLED = 0

 PARAMETER C_BUS2CORE_CLK_RATIO = 1

 PARAMETER C_TEMAC_TYPE = 0

 PARAMETER C_TEMAC0_PHYADDR = 0b00001

 PARAMETER HW_VER = 2.03.a

 PARAMETER C_BASEADDR = 0x81C00000

 PARAMETER C_HIGHADDR = 0x81C7FFFF

 PARAMETER C_TEMAC0_TXCSUM = 1

 PARAMETER C_TEMAC0_RXCSUM = 1

 BUS_INTERFACE SPLB = plb_v46_0

 BUS_INTERFACE LLINK0 = Hard_Ethernet_MAC_LLINK0

 PORT TemacIntc0_Irpt = Hard_Ethernet_MAC_TemacIntc0_Irpt

 PORT TemacPhy_RST_n = fpga_0_Hard_Ethernet_MAC_TemacPhy_RST_n_pin

 PORT LlinkTemac0_CLK = clk_100_0000MHzPLL0_ADJUST

 PORT MDC_0 = fpga_0_Hard_Ethernet_MAC_MDC_0_pin

 PORT MDIO_0 = fpga_0_Hard_Ethernet_MAC_MDIO_0_pin

 PORT MGTCLK_P = Hard_Ethernet_MAC_MGTCLK_P

 PORT MGTCLK_N = Hard_Ethernet_MAC_MGTCLK_N

 PORT TXP_0 = Hard_Ethernet_MAC_TXP_0

 PORT TXN_0 = Hard_Ethernet_MAC_TXN_0

 PORT RXP_0 = Hard_Ethernet_MAC_RXP_0

 PORT RXN_0 = Hard_Ethernet_MAC_RXN_0

END

 

BEGIN xps_ll_temac

 PARAMETER INSTANCE = Hard_Ethernet_MAC2

 PARAMETER HW_VER = 2.03.a

 PARAMETER C_BASEADDR = 0x81C80000

 PARAMETER C_HIGHADDR = 0x81CFFFFF

 PARAMETER C_NUM_IDELAYCTRL = 2

 PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X0Y4-IDELAYCTRL_X1Y5

 PARAMETER C_PHY_TYPE = 4

 PARAMETER C_BUS2CORE_CLK_RATIO = 1

 PARAMETER C_TEMAC0_PHYADDR = 0b00011

 PARAMETER C_TEMAC1_ENABLED = 1

 PARAMETER C_TEMAC1_PHYADDR = 0b00100

 PARAMETER C_TEMAC0_TXCSUM = 1

 PARAMETER C_TEMAC0_RXCSUM = 1

 PARAMETER C_TEMAC1_TXCSUM = 1

 PARAMETER C_TEMAC1_RXCSUM = 1

 BUS_INTERFACE SPLB = plb_v46_0

 BUS_INTERFACE LLINK0 = Hard_Ethernet_MAC2_LLINK0

 BUS_INTERFACE LLINK1 = Hard_Ethernet_MAC2_LLINK1

 PORT TemacIntc0_Irpt = Hard_Ethernet_MAC2_TemacIntc0_Irpt

 PORT TemacIntc1_Irpt = Hard_Ethernet_MAC2_TemacIntc1_Irpt

 PORT TemacPhy_RST_n = Hard_Ethernet_MAC2_TemacPhy_RST_n

 PORT MGTCLK_P = Hard_Ethernet_MAC2_MGTCLK_P

 PORT MGTCLK_N = Hard_Ethernet_MAC2_MGTCLK_N

 PORT LlinkTemac0_CLK = clk_100_0000MHzPLL0_ADJUST

 PORT LlinkTemac1_CLK = clk_100_0000MHzPLL0_ADJUST

 PORT TXP_0 = Hard_Ethernet_MAC2_TXP_0

 PORT TXN_0 = Hard_Ethernet_MAC2_TXN_0

 PORT RXP_0 = Hard_Ethernet_MAC2_RXP_0

 PORT RXN_0 = Hard_Ethernet_MAC2_RXN_0

 PORT TXP_1 = Hard_Ethernet_MAC2_TXP_1

 PORT TXN_1 = Hard_Ethernet_MAC2_TXN_1

 PORT RXP_1 = Hard_Ethernet_MAC2_RXP_1

 PORT RXN_1 = Hard_Ethernet_MAC2_RXN_1

 PORT MDC_0 = Hard_Ethernet_MAC2_MDC_0

 PORT MDC_1 = Hard_Ethernet_MAC2_MDC_1

 PORT MDIO_0 = Hard_Ethernet_MAC2_MDIO_0

 PORT MDIO_1 = Hard_Ethernet_MAC2_MDIO_1

END

 

 

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Observer gi4you
Observer
7,942 Views
Registered: ‎09-24-2009

Re: Multiple SGMII Ethernet PHYs at ML507

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Hello,

 

Thanks for nice example.

 

When i configure "SGMII" for SFP it has succesfully generate bitstream file.

But when i configure "1000BASS-X" for EMAC2, i found of time constranit file errors.

 

Did you have any sugessions for fixing problems ?

 

---------------------------------------------------------------------------------------------------------------

ERROR:ConstraintSystem:59 - Constraint <INST
   "Hard_Ethernet_MAC2/Hard_Ethernet_MAC2/V5HARD_SYS.I_TEMAC/DUAL_SGMII_FX.I_EMA

C_TOP/GTX_DUAL_1000X_inst/GTX_1000X/tile0_rocketio_wrapper_gtx_i/gtx_dual_i"
   LOC = "GTX_DUAL_X0Y5";> [system.ucf(393)]: INST
   "Hard_Ethernet_MAC2/Hard_Ethernet_MAC2/V5HARD_SYS.I_TEMAC/DUAL_SGMII_FX.I_EMA
   C_TOP/GTX_DUAL_1000X_inst/GTX_1000X/tile0_rocketio_wrapper_gtx_i/gtx_dual_i"
   not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <INST
   "Hard_Ethernet_MAC2/Hard_Ethernet_MAC2/V5HARD_SYS.I_TEMAC/DUAL_SGMII_FX.I_EMA

C_TOP/v5_emac_wrapper/v5_emac" LOC = "TEMAC_X0Y1";> [system.ucf(394)]: INST
   "Hard_Ethernet_MAC2/Hard_Ethernet_MAC2/V5HARD_SYS.I_TEMAC/DUAL_SGMII_FX.I_EMA
   C_TOP/v5_emac_wrapper/v5_emac" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:Xflow - Program ngdbuild returned error code 2. Aborting flow execution...
make: *** [__xps/system_routed] Error 1

 

 

Thank you,

Kiman

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Observer gi4you
Observer
7,937 Views
Registered: ‎09-24-2009

Re: Multiple SGMII Ethernet PHYs at ML507

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Hello,

 

I have modified for EMAC2 "1000BASE-X" SFP port.

 

INST "Hard_Ethernet_MAC2/Hard_Ethernet_MAC2/V5HARD_SYS.I_TEMAC/*_FX.I_EMAC_TOP/GTX_DUAL_1000X_inst/GTX_1000X/tile0_rocketio_wrapper_gtx_i/gtx_dual_i" LOC = "GTX_DUAL_X0Y5";
INST "Hard_Ethernet_MAC2/Hard_Ethernet_MAC2/V5HARD_SYS.I_TEMAC/*_FX.I_EMAC_TOP/v5_emac_wrapper/v5_emac" LOC = "TEMAC_X0Y1";

 

 

After that i tried to testing lwIP TCP echo server.

 

-----lwIP TCP echo server ------
TCP packets sent to port 6001 will be echoed back
Board IP: 192.168.90.2
Netmask : 255.255.255.0
Gateway : 192.168.90.168
auto-negotiated link speed: 100
TCP echo server started @ port 7

 

 

---------------------

Two problems:

1) link speed  is 100 Mbps

2) Not response of ping test.

 

Please let me know any commant .

 

Thanks,

Kiman

 

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