UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
1,332 Views
Registered: ‎11-17-2016

Port direction mismatch for port 'tx_unfout_0' in 40G Ethernet subsystem 2.1 IP

I've tried making a MAC LOOPBACK project in Vivado 2017.1 with IP integrator. I've used '40G ETHERNET SUBSYSTEM v2.1' IP with datapath interface selected to 256bit Regular AXI4 stream. But during synthesis, it shows the error: [Synth 8-547] port direction mismatch for port 'tx_unfout_0' in bd.hdl file. 

 

Then I've changed the design with datapath interface selected to 128bit STRADDLED AXI4 STREAM. With this, the design is synthesizing without any error.

 

Then I've opened the IP example design (Here the IP is instantiated, not used in IP INTEGRATOR) with 256bit Regular AXI4 stream and it is also synthesizing without any error. 

 

Why I'm not able to synthesize the same design which is made with IP integrator? 'tx_unfout' is an output from the IP, and why it is showing 'port direction mismatch' error, when the bd.hdl file is also created by the tool itself?

 

In the product guide, this port is listed under '128-bit Straddled AXI4-Stream User Interface Signals' and it is mentioned there that, "Ports under this section will be available when Ethernet MAC+PCS/PMA with the 128-bit Straddle Packet AXI4-Stream option is selected from the Configuration tab." No such signal is mentioned under 256-bit Regular AXI4-Stream User Interface Signals in the document, but the same port appears in the IP. 

 

How can I resolve this Issue? I want to make the design in IP integrator with 256bit Regular AXI4 stream itself.

unfout.JPG
0 Kudos