UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Reply

Problem with simulating Aurora Core, non used signals throwing errors

Accepted Solution Solved
Highlighted
Newbie
Posts: 3
Registered: ‎03-13-2018
Accepted Solution

Problem with simulating Aurora Core, non used signals throwing errors

I was handed a project in which a functional set of Aurora cores (2 on a single board) were correctly working and communicating with other boards. For some reason, this project had no testbench or any other form of simulation, so I am trying to create a simulation where the two Aurora cores communicate with each other on a single board. I created a test bench of the top level wrapper which contains both cores, and some other logic for driving them. Right now the only thing in that test bench is the top level wrapper instantialized as a component, and a port map connecting the inputs to some signals.

 

When I try to run this simulation, it gives me an error telling me "formal drpaddr_in has no actual or default value [C:/..../duplex_channel_aurora_8b10b_0_1.vhd:130]", and a few other drp signals. 

 

These signals aren't even in my project. As I understand it, they're normally only made available when the GT DRP Interface option is enabled, but it is not enabled for this project, and these signals do not appear in my block diagram. Why is Vivado telling me to drive these signals if they aren't even part of the wrapper, let alone part of the project?


Accepted Solutions
Posts: 2,610
Kudos: 325
Solutions: 237
Registered: ‎02-16-2010

Re: Problem with simulating Aurora Core, non used signals throwing errors

There was a known issue with Aurora 8B10B v10.3/Aurora 64B66B v9.3

Check this AR.
https://www.xilinx.com/support/answers/63338.html
------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------

View solution in original post


All Replies
Voyager
Posts: 1,056
Registered: ‎02-24-2014

Re: Problem with simulating Aurora Core, non used signals throwing errors

you'll have to dig down into the wrapper around the GT core, and place zeros on the DRP interface, even if it's not used.  Simulation (and synthesis) really doesn't like it when inputs to a block are dangling, and have no default values defined.

Don't forget to close a thread when possible by accepting a post as a solution.
Posts: 2,610
Kudos: 325
Solutions: 237
Registered: ‎02-16-2010

Re: Problem with simulating Aurora Core, non used signals throwing errors

There was a known issue with Aurora 8B10B v10.3/Aurora 64B66B v9.3

Check this AR.
https://www.xilinx.com/support/answers/63338.html
------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
Newbie
Posts: 3
Registered: ‎03-13-2018

Re: Problem with simulating Aurora Core, non used signals throwing errors

So I should edit the IP's source code? I had considered this, but it felt like a poor solution. Maybe I'll just enable the ports and tie them to a constant block so that it's still contained in my design.
Newbie
Posts: 3
Registered: ‎03-13-2018

Re: Problem with simulating Aurora Core, non used signals throwing errors

Thanks venkata. That looks exactly like my problem. I'll try this solution in a bit and report back if it works.