03-12-2018 02:14 AM
I am using JESD204B IP core as a receiver(subclass 1).I found that the ILA can capture the SYSREF signal（one-shot mode）, the K28.5 character is right(0xbc) while the sync signal doesn't assert .like the picture show:
However when I read the Sync Status register(0x038),the value is 0x0，which means 'no SYSREF event has been captured'，but it did captured by the ILA，can anyone tell me why?
03-13-2018 02:04 AM
for 204b subclass, the sysref should be captured by the IP core clock, since the register shows that no SYSREF event has been captured, this means the IP core does not capture sysref. ILA captureing sysref does not mean that sysref is sampled by IP core clock.
03-13-2018 06:56 PM
I found that there may be something wrong with the JESD204B core clock.
I found that when I set the Lane rate with 4.9152Gbps，in this case the JESD204B reference clock and core clock are both 122.88MHz.That means I only need reference clock. I found in this case the JESD204B can alway run right.
However when the Lane rate is 1.2288Gbps,the JESD204B reference clock is 122.88MHz and the core clock is 30.72MHz.In this case I need both clocks.However the IP core can not dessert sync signal.
So I guess there may be something wrong with the core clock.
My core clock and reference clock are both from the clock distribution chip.The reference clock connect to the pin MGTREFCLK.The core clock connect to the pin MRCC (HR IO bank) . Is this right？
What constraints should I add for the core clock?