01-14-2018 01:33 PM - edited 01-15-2018 01:30 AM
In my project I want to use CPRI interface in loopback mode on Ultrascale+ ZCU102 board, featured with four SFP+ and GTH transceivers in fpga device.
I need to transmit IQ samples at 15.7 Gbit/s over CPRI link in loopback mode, which forces me to use two GTH transceivers. In documentation for CPRI v8.7 I found information on how to share clocking and tx-alignment resources between up to 4 CPRI cores, operating at the same rate. In Vivado simulation I see that in this case each CPRI starts IQ transmission simultaneously (i.e. iq_tx_enable signal)
Is there any standard means to synchronize data at the RX side as well? On reception I need to reassemble data, which have been divided between two CPRI blocks. I use rx_chk module from example design for each CPRI and I monitor number of received frames. Numbers are different all the time.
My setup is similar to one depicted in pb047-cpri-gateway.pdf (I have 2 cpri links in loopback):
How can I align received data back? I'm thinking about some buffering solution... Or shall I measure difference in cable latency, and try to compensate it with some delay primitives? BTW, cables and SFP+ transceivers are identical.
I'm new to CPRI, any advise is highly appreciated.
01-24-2018 01:28 PM - edited 01-24-2018 01:36 PM
at RX side, basic_frame_first_word is used to align the I/Q data, also you can use one RX recovery clock to drive RX refclk of 4 lanes, so all the channels are running at the same data rate.
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04-11-2018 07:33 AM
Thanks for your answer.
As you adviced, on RX side we use recclk from the "master" lane to generate refclk for all CPRIs. Also we use basic_frame_first_word signals from each of CPRIs to know BF boundaries, we pass the received data to FIFOs and we read from these FIFOs (which have to be properly sized) once all of them are not empty.
Thanks for help.