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Adventurer
Adventurer
1,116 Views
Registered: ‎03-31-2017

Synchronous 10G MACs in one quad/incorrect PCS/PMA docs?

I'm trying to generate 4 synchronous 10G Ethernet MACs in a single GTH quad, with a single common rx/tx clock (presumably this is possible?). I'm using the internal physical I/F to the 10G PCS/PMA.

 

This is covered on pages 99/100 of the PCS/PMA doc (PG068), with fig 3-23. Unfortunately there's very little detail (much less than for the 1G PCS/PMA), and it seems to be wrong. Page 99 says:

 

Where up to four 10GBASE-R/KR cores are required which are all in the same GT_QUAD on the target device, you should generate one core with Include Shared Logic in core selected and a second core with Include Shared Logic in example design selected.

 

Fig 3-23 shows one core A (shared logic in core/SLIC), connected to 3 core B's (shared logic in example design/SLIE). This doesn't seem to be right. The SLIC component doesn't have a txoutclk port, which is needed to drive the shared clock and reset component. Fig 3-23 shows both txoutclk and the shared clock block as internal to core A.

 

What's the right way to do this? Do I actually need 4 SLIE components (and no SLIC), with one shared clock block? And do I then choose the txoutclk from one of these SLIEs as the clock input to the shared clock block? Is there a more detailed and/or correct version of Fig 3-23 anywhere? Thanks.

 

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6 Replies
Xilinx Employee
Xilinx Employee
1,110 Views
Registered: ‎02-06-2013

Re: Synchronous 10G MACs in one quad/incorrect PCS/PMA docs?

Hi

 

Which device are you targeting and is this in BASE_R or BASE_KR mode?

 

You need to use one core with Shared logic in example design and 3 with Shared logic in Example design.

 

Have you generated the cores with these options and see any difference in the top level wrappers generated?

Regards,

Satish

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Adventurer
Adventurer
1,081 Views
Registered: ‎03-31-2017

Re: Synchronous 10G MACs in one quad/incorrect PCS/PMA docs?

Hi Satish - this is for V7 (xc7vx690). Currently, two MACs are 10GBASE-R, and 2 are 10GBASE-KR - is that a problem? I'm looking at changing them all to 10GBASE-R anyway.

 

So, basically, all cores with shared logic in example design? Would you mind checking the attached diagram? Thank you.

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Xilinx Employee
Xilinx Employee
1,054 Views
Registered: ‎05-01-2013

Re: Synchronous 10G MACs in one quad/incorrect PCS/PMA docs?

The diagram looks OK to me. You can do functional simulation to verify your design.

What's your problem?

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Adventurer
Adventurer
1,041 Views
Registered: ‎03-31-2017

Re: Synchronous 10G MACs in one quad/incorrect PCS/PMA docs?

No problem, except that the description in PG068 is wrong, and I just wanted a sanity check on whether this is possible and whether my diagram was correct. I haven't done functional sims yet - should be a couple of days - I'll post back whether they're Ok or not. Thanks.

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Xilinx Employee
Xilinx Employee
1,027 Views
Registered: ‎05-01-2013

Re: Synchronous 10G MACs in one quad/incorrect PCS/PMA docs?

I think, PG068 wants to say that the shared logic in example design of other 3 cores can be removed and these 3 cores just share the core's clocks whose shared logic in core.

It's just the same as your design. If you generate all 4 cores shared logic in example design, the project is more flexible.

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Xilinx Employee
Xilinx Employee
1,020 Views
Registered: ‎02-06-2013

Re: Synchronous 10G MACs in one quad/incorrect PCS/PMA docs?

7 Series devices use synchronous gearbox and it is ok to share the txoutclk and it wont cause any issue's when you share it for all the cores in the quad
Regards,

Satish

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