09-13-2017 03:43 AM
I'm trying to generate 4 synchronous 10G Ethernet MACs in a single GTH quad, with a single common rx/tx clock (presumably this is possible?). I'm using the internal physical I/F to the 10G PCS/PMA.
This is covered on pages 99/100 of the PCS/PMA doc (PG068), with fig 3-23. Unfortunately there's very little detail (much less than for the 1G PCS/PMA), and it seems to be wrong. Page 99 says:
Where up to four 10GBASE-R/KR cores are required which are all in the same GT_QUAD on the target device, you should generate one core with Include Shared Logic in core selected and a second core with Include Shared Logic in example design selected.
Fig 3-23 shows one core A (shared logic in core/SLIC), connected to 3 core B's (shared logic in example design/SLIE). This doesn't seem to be right. The SLIC component doesn't have a txoutclk port, which is needed to drive the shared clock and reset component. Fig 3-23 shows both txoutclk and the shared clock block as internal to core A.
What's the right way to do this? Do I actually need 4 SLIE components (and no SLIC), with one shared clock block? And do I then choose the txoutclk from one of these SLIEs as the clock input to the shared clock block? Is there a more detailed and/or correct version of Fig 3-23 anywhere? Thanks.
09-13-2017 03:56 AM
Which device are you targeting and is this in BASE_R or BASE_KR mode?
You need to use one core with Shared logic in example design and 3 with Shared logic in Example design.
Have you generated the cores with these options and see any difference in the top level wrappers generated?
09-13-2017 07:27 AM
09-13-2017 07:11 PM
The diagram looks OK to me. You can do functional simulation to verify your design.
What's your problem?
09-14-2017 12:11 AM
No problem, except that the description in PG068 is wrong, and I just wanted a sanity check on whether this is possible and whether my diagram was correct. I haven't done functional sims yet - should be a couple of days - I'll post back whether they're Ok or not. Thanks.
09-14-2017 08:13 PM
I think, PG068 wants to say that the shared logic in example design of other 3 cores can be removed and these 3 cores just share the core's clocks whose shared logic in core.
It's just the same as your design. If you generate all 4 cores shared logic in example design, the project is more flexible.
09-15-2017 03:36 AM