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Scholar dpaul24
Scholar
7,938 Views
Registered: ‎08-07-2014

Timing failure in use of LogiCORE IP GMII to RGMII v2.0

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Hello,

 

I am having problems in meeting the timing constrains of two instances of the IP GMII to RGMII v2.0.  Please see the screen-shot. Also attached is the xdc I am using.

timing_sum.jpg

 

I have referred to the GMII to RGMII v4.0, PG160 November 18, 2015, docu for building the xdc file for my design.

 

Please help!

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gmii_crossover_timing_err.jpg
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1 Solution

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Scholar dpaul24
Scholar
14,126 Views
Registered: ‎08-07-2014

Re: Timing failure in use of LogiCORE IP GMII to RGMII v2.0

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Thanks

 

I have already used the Xilinx IDELAY primitives and it has solved the issue. Setting the proper IDELAY_VALUE was the key.

Suprisingly the XDC was so simple thereafter, no i/p delays and o/p delays were required to be specified.

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FPGA enthusiast!
All PMs will be ignored
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7 Replies
Scholar dpaul24
Scholar
7,924 Views
Registered: ‎08-07-2014

Re: Timing failure in use of LogiCORE IP GMII to RGMII v2.0

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Hello,

 

I have been playing around with my XDC file and have managed to get rid of the errors mentioned above.

 

However there are still some critical warning messages.

set_op_delay__warning.jpg

 

Is it necessary to set i/p and o/p delays for the *_rgmii_rx* and *_rgmii_tx*?

 

If yes, should I look into the data sheet of the Marvell PHY chips for the delay values?

 

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FPGA enthusiast!
All PMs will be ignored
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Xilinx Employee
Xilinx Employee
7,618 Views
Registered: ‎02-06-2013

Re: Timing failure in use of LogiCORE IP GMII to RGMII v2.0

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Hi

 

Check if the clock mentioned in the constraints exists from the implemented designa and if necessary correct the path.

 

You can also try varying the idelay tap values to meet the timing.

Regards,

Satish

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Scholar dpaul24
Scholar
14,127 Views
Registered: ‎08-07-2014

Re: Timing failure in use of LogiCORE IP GMII to RGMII v2.0

Jump to solution

Thanks

 

I have already used the Xilinx IDELAY primitives and it has solved the issue. Setting the proper IDELAY_VALUE was the key.

Suprisingly the XDC was so simple thereafter, no i/p delays and o/p delays were required to be specified.

--------------------------------------------------------------------------------------------------------
FPGA enthusiast!
All PMs will be ignored
--------------------------------------------------------------------------------------------------------
0 Kudos
Visitor chen.lh
Visitor
4,408 Views
Registered: ‎08-04-2016

Re: Timing failure in use of LogiCORE IP GMII to RGMII v2.0

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hello.i use the GMII to RGMII IP also reference to "http://www.fpgadeveloper.com/2015/12/using-axi-ethernet-subsystem-and-gmii-to-rgmii-in-a-multi-port-ethernet-design.html". When i use PC to Ping my customize board, it can ping successfully,however,it always loss package. i don not know what may make this happen.

the xdc file are also copy from the web link(FPGA Developer), and from PG160 manual. however, when i generate bitstream, it failed to meet timing requirement.

 

Timing.png
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Xilinx Employee
Xilinx Employee
4,404 Views
Registered: ‎02-06-2013

Re: Timing failure in use of LogiCORE IP GMII to RGMII v2.0

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Hi

 

Have you tried varying the idelay tap values to fix the timing errors?

Regards,

Satish

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Visitor chen.lh
Visitor
4,374 Views
Registered: ‎08-04-2016

Re: Timing failure in use of LogiCORE IP GMII to RGMII v2.0

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yes i did. the primitive value is 16, i changed it from 12 to 22. i found when the hold time is meet the setup time failed again, inverse, when the setup time is meet, the hold time failed again.
As the board is a customized board, is this has to use special I/O ports(like HR or HP)? i use ZC7020 and select bank35 and voltage is 1.8V.
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Scholar dpaul24
Scholar
4,286 Views
Registered: ‎08-07-2014

Re: Timing failure in use of LogiCORE IP GMII to RGMII v2.0

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Hi Chen,

 

This might help you, an alternative...

 

Initially I was using the IDELAY modules to set up the delays. But now not.

I use set_input_delay and set_output_delay in my xdc to constrain my design.

You might try this approach.

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FPGA enthusiast!
All PMs will be ignored
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