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Observer micrelrogerlo
Observer
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Registered: ‎09-18-2013

Transceiver for 2.5G SGMII

Recently I am working on 2.5G SGMII validation using 3rd party PCS IP and transceiver from Xilinx IP generated from UltraScale FPGAs Transceivers Wizard (1.7). Although the SGMII design (PCS IP + Transceiver IP from Xilinx) is able to pass RTL simulation which includes SGMII link, auto-negotiation and packet transfer tests, the generated FPGA bit file is unable to get linkup in FPGA emulation.  (Note: We have two FPGA s connected back to back.) We have used a similar approach running on two Virtex-7 devices and it has been proven working in 2.5G SGMII link and auto-negotiation. However, we got the SGMII link issue after been upgraded to UltraScale FPGA device.

I wonder if the transceiver I configured is not correct. Could someone help to indicate what transceiver I should use to serve my purpose?

The following is the configuration data specified in UltraScale FPGAs Transceivers Wizard (1.7):

BASIC section: start from scratch: GTH :

Transmitter: 3.125; CPLL; 0; 125; Raw; 20; 20; Enable; TXOUTCLKPMA; Custom

Receiver: 3.125; CPLL; 0; 125; Raw; 20; 20; Enable; RXOUTCLKPMA; 20; Auto; AC; programmable; 800; 0; 0

Physical Resource:  GTHE3_CH: Bank: 221; Data pins:BC3, BC4, BC7, BC8

Optional Feature:  no update (use default value)

Structural Options: no update (use default value)

 

       Is there anything missing or wrong in Transceiver configuration shown above for supporting 2.5G SGMII?

 

 

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