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Registered: ‎11-28-2018

Ultrascale 100G ethernet FIFO timing error

Hi

I implement   FIFO  inout from LBUS signal.

But timing error has occurred.

Setup error that FIFO  form RDCK to RDEN.

 

 

 

wr_en changed by txusrclk2_0.

rd_en changed by txusrclk2_1.

fifo  core instace is below.

din is 1st LBUS out signal.

dout is 2nd LBUS in signal.

fifo_generator_0 FIFO_0
(
.srst(sys_reset),
.wr_clk(txusrclk2_0),
.rd_clk(txusrclk2_1),
.din(din),
.wr_en(wr_en),
.rd_en(rd_en),
.dout(dout),
.full(full),
.empty(empty),
.wr_rst_busy(),
.rd_rst_busy()
);

 

Does anyone advise me?

   

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