UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
137 Views
Registered: ‎12-10-2018

Ultrascale+ 100G ethernet IP

Dear Sir/Mam,

                  I need a example design for 100G Ethernat, So any one please .....??

Currently I am ther user of Zynq Ultrascale+ 102 evaluation board. So, I want to test this with another same kit.

 

 

Brijendra

0 Kudos
2 Replies
Xilinx Employee
Xilinx Employee
109 Views
Registered: ‎05-01-2013

回复: Ultrascale+ 100G ethernet IP

You can create an IP core example design in Vivado directly.

The example has the top module to run Implement and run simulation directly.

0 Kudos
99 Views
Registered: ‎12-10-2018

回复: Ultrascale+ 100G ethernet IP

Dear Sir/Mam,

                With regards, I would like to tell you that i have generated the project but getting 16 critical warning. and unable to generate BIT STREAM file.

here i am attaching .xdc file.  .XDC file i modified according to XCZU21DR-1156 FPGA.

 

### -----------------------------------------------------------------------------
### CMAC example design-level XDC file
### -----------------------------------------------------------------------------

create_clock -period 10.000 [get_ports init_clk]
set_property IOSTANDARD LVCMOS18 [get_ports init_clk]

 

### Any other constraints can be added here

set_property PACKAGE_PIN T28 [get_ports "gt_ref_clk_p"]
set_property PACKAGE_PIN T29 [get_ports "gt_ref_clk_n"]

set_property PACKAGE_PIN R30 [ get_ports "gt0_rxp_in" ]
set_property PACKAGE_PIN R31 [ get_ports "gt0_rxn_in" ]
set_property PACKAGE_PIN N30 [ get_ports "gt1_rxp_in" ]
set_property PACKAGE_PIN N31 [ get_ports "gt1_rxn_in" ]
set_property PACKAGE_PIN L30 [ get_ports "gt2_rxp_in" ]
set_property PACKAGE_PIN L31 [ get_ports "gt2_rxn_in" ]
set_property PACKAGE_PIN J30 [ get_ports "gt3_rxp_in" ]
set_property PACKAGE_PIN J31 [ get_ports "gt3_rxn_in" ]
set_property PACKAGE_PIN P34 [ get_ports "gt0_txn_out" ]
set_property PACKAGE_PIN P33 [ get_ports "gt0_txp_out" ]
set_property PACKAGE_PIN M34 [ get_ports "gt1_txn_out" ]
set_property PACKAGE_PIN M33 [ get_ports "gt1_txp_out" ]
set_property PACKAGE_PIN K34 [ get_ports "gt2_txn_out" ]
set_property PACKAGE_PIN K33 [ get_ports "gt2_txp_out" ]
set_property PACKAGE_PIN H34 [ get_ports "gt3_txn_out" ]
set_property PACKAGE_PIN H33 [ get_ports "gt3_txp_out" ]

 

set_property SEVERITY {Warning} [get_drc_checks UCIO-1]

 

 

 

Also here i am attaching screanshot for vivado project  output and log file.

 

Please suggest me where, i am wrong............

 

Brijendra

 

 

 

0 Kudos