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219 Views
Registered: ‎11-28-2018

Ultrascale 100G ethernet implement error

I trying to from sample design to board design on Ultrascale 100G ethernet.

But implement error has occured.

------->error message is below

ERROR: [Place 30-415] IO Placement failed due to overutilization. This design contains 1103 I/O ports
180  while the target  device: xcvu190 package: flgb2104, contains only 1068 available user I/O. The target device has 1084 usable I/O pins of which 1    6 are already occupied by user-locked I/Os.
181  To rectify this issue:
182  1. Ensure you are targeting the correct device and package.  Select a larger device or different package if necessary.
183  2. Check the top-level ports of the design to ensure the correct number of ports are specified.
184  3. Consider design changes to reduce the number of I/Os necessary.

------->xdc file is below

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### -----------------------------------------------------------------------------
### CMAC example design-level XDC file
### -----------------------------------------------------------------------------

create_clock -period 10.000 [get_ports init_clk]
set_property IOSTANDARD LVCMOS18 [get_ports init_clk]

set_property PACKAGE_PIN D40  [ get_ports "sys_rst" ]
set_property IOSTANDARD LVCMOS12 [ get_ports "sys_rst" ]


### Transceiver Reference Clock Placement
### Transceivers should be adjacent to allow timing constraints to be met easily.
### Full details of available transceiver locations can be found in the appropriate
### Transceiver User Guide, or use the Transceiver Wizard.

### These are sample constraints, please use correct constraints for your device
### As per GT recommendation, gt_ref_clk should be connected to the middle quad

### Incase of VCU108-REV-1.0 Evaluation board with xcvu095-ffva2104-2-e device,
### if user selects CAUI10 GTY default gui configuration with CMAC core as CMAC_SITE_X0Y0
### and GT group X0Y4~X0Y13, the gt_ref_clk pin location is given below
### For other configuration / CMAC and GT locations, update the gt_ref_clk pin location accordingly
### and un-comment the below line
#set_property PACKAGE_PIN AK38 [get_ports gt_ref_clk_p]

 

### Change these IO constraints as per your board and device
### For better placement, please LOC the IO's in the same GT SLR region

### Below IO Loc XDC constraints are for VCU108-REV-1.0 Evaluation board
### with xcvu095-ffva2104-2-e-es2 device

### For init_clk input pin assignment, if single-ended clock is not available
### on the board, user has to instantiate IBUFDS in Example Design to convert
### the differential clock to single-ended clock and make the necessary changes
#set_property LOC AT19 [get_ports init_clk]
#set_property LOC AT18 [get_ports sys_reset]
#set_property LOC AP18 [get_ports send_continuous_pkts]
#set_property LOC AU17 [get_ports lbus_tx_rx_restart_in]
#set_property LOC AP20 [get_ports tx_done_led]
#set_property LOC AU21 [get_ports tx_busy_led]
#set_property LOC AN18 [get_ports rx_gt_locked_led]
#set_property LOC AN17 [get_ports rx_aligned_led]
#set_property LOC AN19 [get_ports rx_done_led]
#set_property LOC AP19 [get_ports rx_data_fail_led]
#set_property LOC AM16 [get_ports rx_busy_led]

set_property IOSTANDARD LVCMOS18 [get_ports sys_reset]
set_property IOSTANDARD LVCMOS18 [get_ports send_continuous_pkts]
set_property IOSTANDARD LVCMOS18 [get_ports lbus_tx_rx_restart_in]
set_property IOSTANDARD LVCMOS18 [get_ports tx_done_led]
set_property IOSTANDARD LVCMOS18 [get_ports tx_busy_led]
set_property IOSTANDARD LVCMOS18 [get_ports rx_gt_locked_led]
set_property IOSTANDARD LVCMOS18 [get_ports rx_aligned_led]
set_property IOSTANDARD LVCMOS18 [get_ports rx_done_led]
set_property IOSTANDARD LVCMOS18 [get_ports rx_data_fail_led]
set_property IOSTANDARD LVCMOS18 [get_ports rx_busy_led]

### Any other constraints can be added here

 

I attached verilog source.

Does anyone help me?

 

 

 

 

 

 

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3 Replies
Voyager
Voyager
137 Views
Registered: ‎10-23-2018

Re: Ultrascale 100G ethernet implement error

@kyosuke.yoshizu

You have exceed your budget on the number of available ports... Try to reduce that usage (or implement on more capable hardware)

Please mark as solution accepted.

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99 Views
Registered: ‎01-08-2012

Re: Ultrascale 100G ethernet implement error

The 100G Ethernet core only requires a very small number of ports that connect to FPGA I/O pins.  There's the transceivers, the clocks, the small number of low speed I/O for the (e.g.) QSFP socket.  That's it.

    This design contains 1103 I/O ports

I suspect you connected the LBUS ports of the IP to FPGA I/O pins, which adds roughly 1k pins.  These LBUS connections are meant to be terminated inside the FPGA fabric, typically by being connected to some other IP that generates or receives packets.

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88 Views
Registered: ‎11-28-2018

Re: Ultrascale 100G ethernet implement error

The cause turned out.
It is because one IP core was doubly defined in two logics.

 

Thanks.

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