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Observer mmohiuddin
Observer
180 Views
Registered: ‎09-18-2017

Verifying JESD204B is Transmitting K28.5 Characters

Hi all,

I'm using the Xilinx JES204B IP (evaluation license) on a Kintex-7 for the TX side of the link, and an AD9173 for the RX side.  I'm having trouble establishing a link in Subclass 0.  Using the IP wizard, I've configured the core to use 2 lanes per link (L=2).  I've placed a chip scope and probed the SYNC~ signal which comes back from the AD9173, which is labeled "p_0_in."  See below:

ila.png

My understanding is that the RX side of the link pulls SYNC~ low while code group sync (CGS) is happening, and SYNC~ will go high each time a lane has completed CGS.  A lane completes CGS when it sees 4 sequential K28.5 characters.  So for L=2, I'd expect to see one high pulse, followed by a rising edge that stays high after that.  However, I'm seeing a sequence of pulses which doesn't make sense to me...what is going on here?  How can I make sure that the TX (Kintex-7) is transmitting K28.5 characters correctly?

I've also recently posted a question about lane number mismatch.  If the L does not match on the TX/RX side of the link, will CGS ever occur correctly?

Mashrur

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2 Replies
Xilinx Employee
Xilinx Employee
108 Views
Registered: ‎10-19-2011

Re: Verifying JESD204B is Transmitting K28.5 Characters

Hi @mmohiuddin ,

The RX signals to the TX that there are errors in the link. This can be frame errors or a link limitation.

Please check that both TX and RX have the same frame configuration. If you are sure this is the case, you might need to check that the link is good in regards to signal integrity.

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Observer mmohiuddin
Observer
92 Views
Registered: ‎09-18-2017

Re: Verifying JESD204B is Transmitting K28.5 Characters

Hi @eschidl,

I figured out the issue.  I believe the SYNC~ pulse train seen in the screenshot is irrelevant, and it's a consequence of the start-up sequence that is going on in the ADI chip.  If any ADI employees come across this post and disagree, feel free to correct me.

The issue ended up being a combination of two things: power supplies and subclass configuration.  Once we configured the chip, the voltages at the chip dropped a little out of spec, just enough to cause things to stop functioning properly.  We also thought that the Xilinx core was configured for subclass 0, but the AXI registers showed subclass 1.  Once these two things were corrected, we saw output from the AD9173.

Thanks for your help! Hopefully this information helps someone out in the future.

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