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Adventurer
Adventurer
1,535 Views
Registered: ‎02-06-2018

Virtex Ultrascale+ 100G Ethernet Subsystem - link down

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Hi

 

I have created the example design for 100G Ethernet subsystem and I confirm that the simulation, near-end PMA and loopback module works on the real hardware. 

 

Now I'm planning to capture the packets generated in the example design on the destination machine running Ubuntu. I have directly connected ports using a copper wire (not optical fiber). The Ethernet link does not go up, any ideas how to debug this issue?

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Adventurer
Adventurer
1,881 Views
Registered: ‎02-06-2018

Re: Virtex Ultrascale+ 100G Ethernet Subsystem - link down

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So the issue was solved by enabling RS-FEC on Xilinx side.

 

on Linux machine, there is a Mellanox ConnectX-4 adapter that it seems has RS-FEC always enabled. In my design, RS-FEC was disabled and by activating it, I could get the link on both switch and also direct connection to Linux machine.

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Adventurer
Adventurer
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Registered: ‎02-06-2018

Re: Virtex Ultrascale+ 100G Ethernet Subsystem - link down

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So, I could get the link established by using a 100G switch between the FPGA and the Linux machine. I'm not sure why the direct connection does not work.
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Xilinx Employee
Xilinx Employee
1,467 Views
Registered: ‎04-16-2008

Re: Virtex Ultrascale+ 100G Ethernet Subsystem - link down

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When connecting directly between FPGA and Linux Machine is the link down on both sides of the link? 

 

Could there be a mismatch in settings? Link will not come up if AN/LT or RS-FEC is enabled on one side of the link, but not the other.

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Adventurer
Adventurer
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Registered: ‎02-06-2018

Re: Virtex Ultrascale+ 100G Ethernet Subsystem - link down

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@ejanney AN/LT and RS_FEC are both disabled in the design.

The link on Linux machine side is down, I'm not sure about FPGA side, How can I check that?

I suspect the linux machine is rejecting the packets due to wrong data format. so I'm writing a Verilog to wrap them in a UDP frame. That being said, I was expecting to at least get the link up. am I missing anything?
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Xilinx Employee
Xilinx Employee
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Registered: ‎04-16-2008

Re: Virtex Ultrascale+ 100G Ethernet Subsystem - link down

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Hi,

 

Link up should be determined by PCS getting block lock (sees valid 64/66bit header) and  alignment (alignment completes such that valid lane markers are seen at same time for all lanes).

 

For Xilinx RX you can look at:

stat_rx_status

stat_rx_block_lock

stat_rx_aligned

stat_rx_synced

 

If Xilinx RX is coming up it maybe that you need to adjust TX drive strength.

 

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Adventurer
Adventurer
1,448 Views
Registered: ‎02-06-2018

Re: Virtex Ultrascale+ 100G Ethernet Subsystem - link down

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@ejanney Thank you! I'll look into that. 

 

What do you mean by "adjusting TX drive strength"?  Is it adjustable? 

 

 

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Xilinx Employee
Xilinx Employee
1,433 Views
Registered: ‎04-16-2008

Re: Virtex Ultrascale+ 100G Ethernet Subsystem - link down

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The GT TX Driver can be modified from default when the CMAC core is generated with GUI option Enable Additional GT Control/Status and DRP Ports selected.  This give you access to:

TXDIFFCTRL

TXPRECURSURSOR

TXPOSTCURSOR

 

see UG578 for more information. 

 

You could also look at running IBERT PRBS testing if link partner supports enabling PRBS testing or a far-end loopback option.

 

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Adventurer
Adventurer
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Registered: ‎02-06-2018

Re: Virtex Ultrascale+ 100G Ethernet Subsystem - link down

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@ejanney Wonderful! Thank you!!
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Adventurer
Adventurer
1,882 Views
Registered: ‎02-06-2018

Re: Virtex Ultrascale+ 100G Ethernet Subsystem - link down

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So the issue was solved by enabling RS-FEC on Xilinx side.

 

on Linux machine, there is a Mellanox ConnectX-4 adapter that it seems has RS-FEC always enabled. In my design, RS-FEC was disabled and by activating it, I could get the link on both switch and also direct connection to Linux machine.

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Visitor ralf.kundel
Visitor
267 Views
Registered: ‎02-19-2018

Re: Virtex Ultrascale+ 100G Ethernet Subsystem - link down

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Hello,

I have a very similar problem:

I have a VCU1525 FPGA board with two DAC calbe and a mellanox ConnextX-4 NIC.

And I have also no link detected in ubuntu ;-)

I also tried to enable the RS-FEC, without success.

 

"Include AN/LT Logic" in "General"--tab is disabled because I have no license for that. However for 100GBASE-SR4 no license should be required.

 

My ethtool config is appended below.

Which IP core settings/ubuntu settings have you used for getting a link?

 

Thanks in advance

Ralf

 

 

Settings for ens1f1:
Supported ports: [ Backplane ]
Supported link modes: 1000baseKX/Full
10000baseKR/Full
40000baseKR4/Full
40000baseCR4/Full
40000baseSR4/Full
40000baseLR4/Full
56000baseKR4/Full
25000baseCR/Full
25000baseKR/Full
25000baseSR/Full
50000baseCR2/Full
50000baseKR2/Full
100000baseKR4/Full
100000baseSR4/Full
100000baseCR4/Full
100000baseLR4_ER4/Full
Supported pause frame use: Symmetric
Supports auto-negotiation: Yes
Supported FEC modes: Not reported
Advertised link modes: 100000baseKR4/Full
100000baseSR4/Full
100000baseCR4/Full
100000baseLR4_ER4/Full
Advertised pause frame use: Symmetric
Advertised auto-negotiation: No
Advertised FEC modes: Not reported
Speed: Unknown!
Duplex: Unknown! (255)
Port: Direct Attach Copper
PHYAD: 0
Transceiver: internal
Auto-negotiation: off
Cannot get wake-on-lan settings: Operation not permitted
Current message level: 0x00000004 (4)
link
Link detected: no

 

 

 

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