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Visitor silane
Visitor
101 Views
Registered: ‎12-24-2018

Vivado IP integrator wrongly modify generated IP

Hi

I'm using EK-U1-VCU118-G evaluation board with XCVU9P FPGA + Vivado 2018.2

I try to implement a simple design in Vivado IP integrator. 2 Ethernet subsystems (10G/25G V2.4) in constant 10G configurations. Both cores will be driven by an "on FPGA" packet generator. Externally these 10G ports are connected together with a crossover connector.

I've used the firefly connector that was supplied with the EVB to make this 10G ethernet crossover connector.

Now I have a problem with the Vivado IP integrator. I've added 2 ethernet subsystems, configured them to bank X1Y14 where the firefly connctor is connected, constant 10G (No Runtime Switchable Mode ), Base-R, DRP port, RX&TX flow control logic etc. Than I used "Run Connection Automation" because I wanted to let Vivado find the suitable clocks to drive these cores (I'm not familiar with the crystal and clock disribution for this EVB).

In case I run this on a block design with just a single ethernet subsystems the Vivado ends the "Run Connection Automation" with no errors but it changes the ethernet IP to 25G, base-KR, removes the flow-control logic, moves the IP to X1Y12 and removes the GT Control/Status and DRP ports that I've configured. This is not what I've asked...

In case I run this on a block design with 2 ethernet subsystems the Vivado ends the "Run Connection Automation" with errors:

apply_bd_automation -rule xilinx.com:bd_rule:board -config { Board_Interface {qsfp1_1x ( QSFP Connector 1 ) } Manual_Source {Auto}} [get_bd_intf_pins xxv_ethernet_0/gt_serial_port]
apply_bd_automation -rule xilinx.com:bd_rule:board -config { Board_Interface {qsfp1_si570_clock ( QSFP Connector 1 ) } Manual_Source {Auto}} [get_bd_intf_pins xxv_ethernet_0/gt_ref_clk]
INFO: [board_rule 100-100] set_property CONFIG.DIFFCLK_BOARD_INTERFACE qsfp1_si570_clock [get_bd_cells /xxv_ethernet_0]
INFO: [board_rule 100-100] create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 qsfp1_si570_clock
INFO: [board_rule 100-100] set_property CONFIG.FREQ_HZ 161132812 /qsfp1_si570_clock
INFO: [board_rule 100-100] connect_bd_intf_net /qsfp1_si570_clock /xxv_ethernet_0/gt_ref_clk
INFO: [board_rule 100-100] set_property CONFIG.FREQ_HZ 161132812 /qsfp1_si570_clock
apply_bd_automation: Time (s): cpu = 00:00:29 ; elapsed = 00:00:27 . Memory (MB): peak = 7848.656 ; gain = 0.000 ; free physical = 54913 ; free virtual = 59101
INFO: [BD 5-455] Automation on '/xxv_ethernet_0/gt_drpclk_0' will not be run, since it is obsolete due to previously run automations
apply_bd_automation -rule xilinx.com:bd_rule:clkrst -config {Clk "New Clocking Wizard (100 MHz)" } [get_bd_pins xxv_ethernet_0/dclk]
apply_bd_automation -rule xilinx.com:bd_rule:board -config { Board_Interface {qsfp1_1x ( QSFP Connector 1 ) } Manual_Source {Auto}} [get_bd_intf_pins xxv_ethernet_1/gt_serial_port]
INFO: [board_rule 100-100] set_property CONFIG.USE_BOARD_FLOW true [get_bd_cells /xxv_ethernet_1]
INFO: [board_rule 100-100] set_property CONFIG.ETHERNET_BOARD_INTERFACE qsfp1_1x [get_bd_cells /xxv_ethernet_1]
INFO: [board_rule 100-100] create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 qsfp1_1x_0
INFO: [board_rule 100-100] connect_bd_intf_net /qsfp1_1x_0 /xxv_ethernet_1/gt_serial_port
apply_bd_automation: Time (s): cpu = 00:00:50 ; elapsed = 00:00:49 . Memory (MB): peak = 7848.656 ; gain = 0.000 ; free physical = 54898 ; free virtual = 59085
apply_bd_automation -rule xilinx.com:bd_rule:board -config { Board_Interface {qsfp1_si570_clock ( QSFP Connector 1 ) } Manual_Source {Auto}} [get_bd_intf_pins xxv_ethernet_1/gt_ref_clk]
ERROR: [board_rule 100-101] Invalid Configuration value "qsfp1_si570_clock" for "Board_Interface".
ERROR: [Common 17-39] 'send_msg_id' failed due to earlier errors.
ERROR: [#UNDEF] Error found in procedure apply_rule.
ERROR: [Common 17-39] 'send_msg_id' failed due to earlier errors.
INFO: [BD 5-145] Automation rule xilinx.com:bd_rule:board was not applied to object gt_ref_clk
INFO: [Common 17-17] undo 'apply_bd_automation -rule xilinx.com:bd_rule:board -config { Board_Interface {qsfp1_si570_clock ( QSFP Connector 1 ) } Manual_Source {Auto}} [get_bd_intf_pins xxv_ethernet_1/gt_ref_clk]'
ERROR: [Common 17-39] 'apply_bd_automation' failed due to earlier errors.
endgroup

Can you please tell what is the issue and why the Vivado modifies the ethernet cores I've configured?

Thank you,

Elad.

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