06-02-2014 07:05 PM
I am new to FPGA pin assignment and would appreciate if some would clear the following:
The .xdc file generated with Aurora IP does not specify the IO Standard also the directions of the pins are not edittable after exporting the .xdc file.
I know the same question was asked on the forum(http://forums.xilinx.com/t5/Connectivity/What-type-of-IO-should-be-used-for-Aurora/td-p/289115), but it was for ISE, which again I expect to be the same for VIVADO virtex7, but since didn't find any document on this, would appreciate if someone could confirm it.
Also why there are no pin mapping in .xdc file as oppose to .ucf file of ISE?
06-02-2014 08:34 PM
You need to specify LOC and IO standards in XDC for all input and output ports of the design in the top level XDC file. Check if you can find some information from this XAPP design guidelines Table2 - http://www.xilinx.com/support/documentation/application_notes/xapp1192-aurora-64b66b-on-kc705.pdf
06-02-2014 08:48 PM
Aurora IP core generates three xdc files-
1. aurora_64b66b_0_ooc.xdc-> Defines timing constraints on INIT_CLK, user_clk,sync_clk &recclk.
2. aurora_64b66b_0_clocks.xdc-> sets false paths on unwanted paths.
3. aurora_64b66b_0.xdc-> Has GT related LOC constraints.
Attached is the snippet of aurora_64b66b_0.xdc. These are the basic constraints generated by the core. Coming to the IOSTANDARD, the user is prohibited from defining the IOSTANDARD for GT, the tool would configure it.
For all other ports like lane_up, channel_up or any other clock related constraints, the expectation is that the user defines them.
If you are looking for a reference/guidnace on how to do this, the xdc file generated with example design would help you. I'm attaching it for your reference.
06-05-2014 05:25 AM