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Visitor sunfh
Visitor
5,741 Views
Registered: ‎11-23-2011

When instantiation a IP core warning:did not attach to <top_module>

     There is some warnings none errors in the period, output 0 al the time while simulating

     This is the warnings accrued when generating:

WARNING:sim:472 - The chosen IP does not support a Verilog behavioral model,
   generating a Verilog structural model instead.
WARNING:coreutil - WARNING: Default charset GBK not supported, using ISO-8859-1
   instead
WARNING:coreutil - WARNING: Default charset GBK not supported, using ISO-8859-1
   instead

     This is the 3 warnings in synthesize:
WARNING:Xst:2211 - "ipcore_dir/ma.v" line 29: Instantiating black box module <ma>.
WARNING:Xst:616 - Invalid property "SYN_BLACK_BOX 1": Did not attach to top_module.
WARNING:Xst:616 - Invalid property "SYN_NOPRUNE 1": Did not attach to top_module.

       What can I do ?

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7 Replies
Teacher rcingham
Teacher
5,734 Views
Registered: ‎09-09-2010

Re: When instantiation a IP core warning:did not attach to <top_module>

What FPGA?
Which version of ISE?
Is the 'ma.v' file included in your ISE project?

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"If it don't work in simulation, it won't work on the board."
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Visitor sunfh
Visitor
5,731 Views
Registered: ‎11-23-2011

Re: When instantiation a IP core warning:did not attach to <top_module>

What FPGA?
Which version of ISE?
Is the 'ma.v' file included in your ISE project?

 
Family:virtex5    Device:xc5vlx30    Version:ise12.3
The 'ma.v' file is alread included in the project,and it is under the topmodule.  
I'm new,I don't quite got the sentance '# ** Warning: Signature field is null!'
Wheath the' warning' when generating IP core is norma?
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Visitor sunfh
Visitor
5,727 Views
Registered: ‎11-23-2011

Re: When instantiation a IP core warning:did not attach to <top_module>

There is something to add:

When using IP core 'Multiply Accumulator' ,the output is 0 all the time

When using IP core 'Accumulator',it works correctly !

 

Both have the warnings put forward before

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Teacher rcingham
Teacher
5,724 Views
Registered: ‎09-09-2010

Re: When instantiation a IP core warning:did not attach to <top_module>

Is there a 'ma.ngc' file?



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"If it don't work in simulation, it won't work on the board."
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Visitor sunfh
Visitor
5,715 Views
Registered: ‎11-23-2011

Re: When instantiation a IP core warning:did not attach to <top_module>

Yes,there is a 'ma.ngc' file under the file 'ipcore_dir'

 

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Xilinx Employee
Xilinx Employee
5,697 Views
Registered: ‎04-06-2010

Re: When instantiation a IP core warning:did not attach to <top_module>

Did you make sure the structural model was compiled by your simulator? The structural model should be named ma.v

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Visitor sunfh
Visitor
5,690 Views
Registered: ‎11-23-2011

Re: When instantiation a IP core warning:did not attach to <top_module>

I did it by the following steps:

Generate a core

Instantiate it,I cut from the templates provided in the VEO file and pasted it into the module

Then simulate it

If there is something lost,Please tell me. Thank you very much!

 

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