06-11-2017 01:20 AM - edited 06-11-2017 01:27 AM
I'm using XAUI in my design connected to a free run LVDS clock in MGTREFCLK pins that scoping shows true dynamic in my custom board. XAUI Lock fail is my problem. Loosing lock with 156.25 MHz clock on kintex7 fpga with vivado tool is main problem but my code has been tested by xilinx platform and the results were perfect. Constraining clock part in my .xdc file consists of LOC records and period constraint and GTX constraints is copied from example design xdc file. When i remove lock asynchronous condition for starting generation and send procedure, every thing is ok by transceiver and other parts of my code. Can any one help me by providing some probably reasons?
06-20-2017 12:15 AM
Check if your reference clock meets the jitter specification required from below AR
Check if the resets are fine and the free running clock to the core is stable before de-asserting the resets.