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Visitor ejmuir
Registered: ‎12-18-2018

ZCU 104 Ethernet Configurations

I am fairly new to the Ultrascale+ platform and I am exploring the different Ethernet configurations on the ZCU104 development board (PS vs PL and the different varieties of each). I have two issues/questions:


When implementing Ethernet using PS and GEM3 (this seems to be the default configuration), is it necessary to include any other IP blocks in the design? It seems from the documentation that implementing GEM3 connects the MAC to the on-board PHY but it is unclear to me if there are any other steps necessary.


In an attempt to implement Ethernet using PL, I realized that the board has no SFP cage and thus I am required to use the on-board RJ-45 connector which is connected to an on-board RGMII PHY. It would seem that when I run block automation, I receive several warnings like this:

WARNING: [board_rule 100-100] Board automation did not generate location constraint for /axi_ethernet_0/rgmii. Users may need to specify the location constraint manually.

for RGMII, MDIO and PHY_Reset on the AXI 1G/2.5G Ethernet Subsystem block, although when I set the constraints manually I receive errors about these pins being unconstrained. Is it possible to interface a PL MAC with the on-board PHY?


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Registered: ‎02-01-2013

Re: ZCU 104 Ethernet Configurations

1) You don't need to include anything (you don't even need a PL design) in order to connect the PSU GEM3 to the onboard PHY.  Assuming the Zynq MP subsystem is configured properly, the PSU provides all of the necessary connectivity.

2) You cannot connect anything in the PL directly to the PSU's MIO pins, which means a PL-based MAC cannot use any onboard resources that connect to the Zynq MP via MIO. If you implement a PL-based MAC, the path to a 1000BASE-T PHY, for example, would have to go through the PL's HP or HR pins. Using an FMC with a PHY is a common way to provide an external Ethernet interface to a PL-based MAC.

-Joe G.

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