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Adventurer
Adventurer
441 Views
Registered: ‎10-17-2018

dclk pin of 10G ethernet subsytem, how to use it?

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Hi, I'm a very newbie in FPGAs but I'm trying to make a 10GBASE-SR design. According to the datasheet, the dclk pins have the following function "Management/DRP clock: this clock can be any rate that is valid for the applicable transceiver drpclk" I have no idea about what is the correct clock I should put here, I'm currently using the coreclk_out (156.25 MHz) but on the IP settings in the PCS/PMA options I'm using 100Mhz for the DRP clock.

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Xilinx Employee
Xilinx Employee
343 Views
Registered: ‎05-01-2013

回复: dclk pin of 10G ethernet subsytem, how to use it?

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How about using the 156.25MHz USER_CLOCK_P/N on VC707?

When you generate the IP core, please modify the DCLK to 156.25 as well

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Xilinx Employee
Xilinx Employee
415 Views
Registered: ‎05-01-2013

回复: dclk pin of 10G ethernet subsytem, how to use it?

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Do you have any external free-running 100MHz clock to use?

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Adventurer
Adventurer
402 Views
Registered: ‎10-17-2018

回复: dclk pin of 10G ethernet subsytem, how to use it?

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No, I don't. I'm generating a differential 156.25Mhz clock and putting into GTX SMA REF Clock in order to use it as the reference clock for the Ethernet subsystem.

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Xilinx Employee
Xilinx Employee
390 Views
Registered: ‎05-01-2013

回复: dclk pin of 10G ethernet subsytem, how to use it?

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You only have the reference clock? Do you have any other free running clock on the board?

What's the device you're using?

 

This DCLK has multiple usage. One is used as the freerun clock for the GT initialization.

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Adventurer
Adventurer
351 Views
Registered: ‎10-17-2018

回复: dclk pin of 10G ethernet subsytem, how to use it?

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I'm using VC707

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Xilinx Employee
Xilinx Employee
344 Views
Registered: ‎05-01-2013

回复: dclk pin of 10G ethernet subsytem, how to use it?

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How about using the 156.25MHz USER_CLOCK_P/N on VC707?

When you generate the IP core, please modify the DCLK to 156.25 as well

Contributor
Contributor
327 Views
Registered: ‎10-29-2018

回复: dclk pin of 10G ethernet subsytem, how to use it?

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Dear Sir,

I am simulating 10G/25G ethernet IP. I have given gt_refclk of 156.25 MHz and dclk of 100 MHz. Then I simulated design , I see tx_clk_out reamains low. Can you please suggest what might be the error in the design? Please find below the verilog code of testbench:

module testbench();
reg dclk;
reg gt_refclk_p;
reg gt_refclk_n;
wire tx_clk_out_0;
wire rx_clk_out_0;
reg sys_reset;
wire gt_refclk_out;

xxv_ethernet_0 your_instance_name (
.dclk(dclk),
.gt_refclk_p(gt_refclk_p),
.gt_refclk_n(gt_refclk_n),
.tx_clk_out_0(tx_clk_out_0),
.rx_clk_out_0(rx_clk_out_0),
.sys_reset(sys_reset),
.rx_reset_0(sys_reset),
.tx_reset_0(sys_reset),
.gt_refclk_out(gt_refclk_out)
);

initial
begin
gt_refclk_p =1;
forever #3200000.000 gt_refclk_p = ~ gt_refclk_p;
end

initial
begin
gt_refclk_n =0;
forever #3200000.000 gt_refclk_n = ~ gt_refclk_n;
end

initial
begin
dclk =1;
forever #5000000.000 dclk = ~ dclk;
end

initial
begin
sys_reset=1;
#5 sys_reset=0;
end

endmodule

Thank you and Regards,

Puja Kumari

Adventurer
Adventurer
315 Views
Registered: ‎10-17-2018

回复: dclk pin of 10G ethernet subsytem, how to use it?

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I'll use it. Thank you :)
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Contributor
Contributor
310 Views
Registered: ‎10-29-2018

回复: dclk pin of 10G ethernet subsytem, how to use it?

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Hi @jamellyf ,

There is some issue in design, so I posted it here.

Regards,

Puja

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Xilinx Employee
Xilinx Employee
288 Views
Registered: ‎05-01-2013

回复: dclk pin of 10G ethernet subsytem, how to use it?

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You can right click on .xci IP core and generate the IP core example design.

You can try the example simulation first.

 

Contributor
Contributor
284 Views
Registered: ‎10-29-2018

回复: dclk pin of 10G ethernet subsytem, how to use it?

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Hi @guozhenp ,

Thank you for responding to my query.

I simulated the example design of 10G/25G Ethernet IP. tx_clk_out always remains low there also. Please see the attached simulation result.

Thank you and Regards,

Puja Kumari

Capture.PNG
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