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Visitor vinishap_65
Visitor
82 Views
Registered: ‎06-20-2019

gt0_qplloutclk_in & gt0_qplloutrefclk_in Generation in SGMII

Hi,

 

   I am working on SGMII in that i saw this two signal " gt0_qplloutclk_in & gt0_qplloutrefclk_in " i don't know how to generate this for my design. 

I am Implementing my design based on Xilinx_Answer_59968_Connecting_TEMAC_and_SGMII_Cores_in_Vivado_for_7-series pdf

I hope someone could tell how to set it.

 

 

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Xilinx Employee
Xilinx Employee
38 Views
Registered: ‎05-01-2013

回复: gt0_qplloutclk_in & gt0_qplloutrefclk_in Generation in SGMII

These signals are GT signals from its QPLL.

Anyhow, it seems that we do provide the example design including the codes.

Please check the attachment in this AR.

https://www.xilinx.com/support/answers/59968.html

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