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Adventurer
Adventurer
7,091 Views
Registered: ‎07-02-2014

how to give DIFFERENTIAL CLOCK (refclk_n , refclk_p)TO 10GBASE_R with shared logic inside the core ??????????????

hai

 

i am interfacing open source 10GEMAC with 10GBASE_R then want to connect to sfp+ on vc 707 Board vc 707 has 200MHZ differential clk , 

 

i have used  10GBASE_R  IP from vivado 2013.3, here the refference clks namely  refclk_n , refclk_p  , these are refference clk signals for the transreceiver but i cant able to understand what and how to give differential clk to this IP

 

Kindly anyone let me know ..  its urgent ..

 

thanks and regards

 


AKRAM

 

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2 Replies
Moderator
Moderator
7,080 Views
Registered: ‎01-15-2008

Re: how to give DIFFERENTIAL CLOCK (refclk_n , refclk_p)TO 10GBASE_R with shared logic inside the core ??????????????

You can refer to the following from page 33 for the reference clock selection and usage

http://www.xilinx.com/support/documentation/user_guides/ug476_7Series_Transceivers.pdf

 

--Krishna

Xilinx Employee
Xilinx Employee
7,074 Views
Registered: ‎07-23-2012

Re: how to give DIFFERENTIAL CLOCK (refclk_n , refclk_p)TO 10GBASE_R with shared logic inside the core ??????????????

Hi Akram,

In VC707, the transceivers associated with the SFP cage lies in quad113. The GTREFCLKs (0&1) of quad 113 comes from SGMII clock oscillator (125 MHz) and SMA clock respectively.

Refer to Table 1-11 of http://www.xilinx.com/support/documentation/boards_and_kits/vc707/ug885_VC707_Eval_Bd.pdf for details.

If you plan to use on board oscillator then you need to set QPLLREFCLKSEL/CPLLREFCLKSEL attribute to choose MGTREFCLK0 i.e. set the attribute to "001" as mentioned in UG476.

If you plan to provide external clock through SMA ports, then you need to choose MGTREFCLK1 by setting QPLLREFCLKSEL/CPLLREFCLKSEL to "010"

Regards,
Krishna
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