07-25-2014 10:45 PM
We are working with two designs
1. KINTEX XC7K70T-FBG676 + MARVELL 88E1111 PHY interface: SGMII
2. KINTEX XC7K325T-FBG900 + MARVELL 88E1111 PHY interface: SGMII
Design 1. is working. The ping is successful without fail while In Design 2, ping takes place randomly. Both designs are implemented in Vivado 2014.1
For debugging the internal PCS loopback is turned on. The loopback is successful in case 1 and failed in case 2. What could be the reason? How should I debug the problem?
07-26-2014 12:51 AM
I would suggest you to cross check the clocks and rests first in the non working design.
07-28-2014 02:46 AM
Can you provide more details like how are testing the ping response.
Is this standalone ethernet loopback at user side design or using upper stack layers build using processor.
What do you mean by PCS loopback is failed,is the link down or not receiving data properly.
You can also refer the debugging section of PG047 for further hardware debug suggestions.