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Participant a4speaker
Participant
10,011 Views
Registered: ‎08-16-2011

problem in aurora example design

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I am using vivado 2013.3 and want to do a loopback of a transceiver core on AC701 board.

 

I generated core with following parameters

lane width = 2 bytes

line rate = 2gbps

GT refclk = 125 MHz

dataflow mode = duplex

interface = framing

flow control = none

 

I generated example design and ran simulation without any modifications in code. 

I ran the simulation for 90 us but  LANE_UP and CHANNEL_UP signals are not asserted.

Is there problem with example design?

 

 

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1 Solution

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Moderator
Moderator
15,412 Views
Registered: ‎02-16-2010

Re: problem in aurora example design

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In VIVADO, here is the way you could launch simulation with Modelsim.
1. Select the path for simulator in VIVADO project settings
2. run compile_simlib for the target device.
run "compile_simlib -help" for example command
The libraries will get compiled to .cache folder
3. launch Behavioral simulation in modelsim similar to the push button flow you do for XSIM
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9 Replies
Xilinx Employee
Xilinx Employee
10,008 Views
Registered: ‎07-23-2012

Re: problem in aurora example design

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This is a known issue. The simulation time got better in 2014.1.

You need to wait till 1000 us for the channel_up in 2013.4

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Participant a4speaker
Participant
9,999 Views
Registered: ‎08-16-2011

Re: problem in aurora example design

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what ? 1000 us? xsim takes 5 minutes to draw even 100 us. SHould i wait for whole day to run sim for 1000 us?

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Xilinx Employee
Xilinx Employee
9,993 Views
Registered: ‎07-23-2012

Re: problem in aurora example design

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Hi A4speaker,

I understand your concern.

This is certainly not a desired output. That is the reason why we are trying to reduce the simulation issue to a minimum possible value.

If you have a possibility, try using Modelsim. It will provide faster output when compared to XSIM simulation in this case.

Regards,
Krishna
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Moderator
Moderator
9,993 Views
Registered: ‎02-16-2010

Re: problem in aurora example design

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Hi,

 

This is because SIM_RESET_SPEEDUP needed to be set to FALSE for production silicon reset requirements. Please refer to page 57 of ug482.

11.jpg

 

Thanks,

Srinadh

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Participant a4speaker
Participant
9,991 Views
Registered: ‎08-16-2011

Re: problem in aurora example design

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so there is no solution execpt to wait?

 

The problem in using modelsim is that i am new to TCL and i read somewhere that you cant simulate design in modelsim with just a click in vivado as was in ISE. I will take much time to run design in modelsim.

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Moderator
Moderator
15,413 Views
Registered: ‎02-16-2010

Re: problem in aurora example design

Jump to solution
In VIVADO, here is the way you could launch simulation with Modelsim.
1. Select the path for simulator in VIVADO project settings
2. run compile_simlib for the target device.
run "compile_simlib -help" for example command
The libraries will get compiled to .cache folder
3. launch Behavioral simulation in modelsim similar to the push button flow you do for XSIM
------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
Participant a4speaker
Participant
9,962 Views
Registered: ‎08-16-2011

Re: problem in aurora example design

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just for your info .... It took 4-5 hours to draw waveform till ...its 1600 us and still no channel up or lane up

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Participant a4speaker
Participant
9,960 Views
Registered: ‎08-16-2011

Re: problem in aurora example design

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and finally they come up at 1635 us after 5 hours on core i7, 8 gb ram. Totally insane :(

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Participant a4speaker
Participant
9,952 Views
Registered: ‎08-16-2011

Re: problem in aurora example design

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VIVADO----> Productivity multiplied

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