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Observer dguisinger
Observer
4,839 Views
Registered: ‎12-26-2009

proper procedure for testing a pair of GTP tranceivers

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I'm looking to see if anyone has a good example for working with GTP / GTX transceivers and testing a board.

 

I've instanciated the CoreGen GTP example design, I've placed the example files into my  test project.

I find if I use the TILE0_PLLLKDET_OUT signal to drive an LED, the LED always shows green whether my crossover cable is plugged in or not. 

I also have found if I use TRACK_DATA_OUT signal to drive the LED, the LED shows red- once again, regardless of the cable connection.

 

I'm assuming the PLLLKDET_OUT signal must be coming from refclk and not the clock recovery.

 

I very well could be misunderstanding the grame_gen / frame_check code as I really can't find any documentation for it.

Both GTP transceivers in the GTP block are connected to SATA ports, which I am tying together with a SATA Crossover cable.

I used the constraints generated by the wizard for the hundred or so GTP settings, the place and route appears to be correct, and other GTP pairs on the board are known good (SGMII and PCIe) so the assumption is I'm just not understanding how to perform a proper test to see that two SerDes in a device can talk over a cross over cable.

 

Am I going about testing the trancievers the correct way, or is it wrong to have both ends running framegen/framecheck code? 

Any other suggestions?

 

Thanks in advance,

Dan

 

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Xilinx Employee
Xilinx Employee
5,201 Views
Registered: ‎01-03-2008

Re: proper procedure for testing a pair of GTP tranceivers

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For board level testing you should use the ChipScope SerialIO Toolkit (aka IBERT)
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Xilinx Employee
Xilinx Employee
5,202 Views
Registered: ‎01-03-2008

Re: proper procedure for testing a pair of GTP tranceivers

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For board level testing you should use the ChipScope SerialIO Toolkit (aka IBERT)
------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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Observer dguisinger
Observer
4,816 Views
Registered: ‎12-26-2009

Re: proper procedure for testing a pair of GTP tranceivers

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Thanks.  That worked.  My SATA ports both looped back great.  I moved to my FX30T version and tried a link between two boards for a USB3 port .. that wasn't so successful but it ends up the cheap chinese firm that made the cable apparently didn't read the A-to-A spec and wired the RX/TX pairs straight-through  *smacks head*...  

 

Is there a reason for the 100MHz limit on the V5  (The V4 shows 210MHz)?  My board is a two-piece design, I got lucky that the second board provided a 60MHz clock; but normally I only have 125MHz, 150MHz, 200MHz, and 250MHz clocks available.  It seems rather stupid to build that limitation into IBERT when a user can't wrap it with his or her own code to setup the appropriate clocks.  Its not like the Virtex-5 isn't capable of using those clock speeds in the DCM and PLLs.  

 

Its the little things like that which really make me want to smack an engineer at times.  I see no reason CLKIN_DIVIDE_BY_2 couldn't have been selectively enabled....

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Xilinx Employee
Xilinx Employee
4,808 Views
Registered: ‎01-03-2008

Re: proper procedure for testing a pair of GTP tranceivers

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I'm not sure what is the reason is behind the limit that you saw, but it is likely a compromise that needed to be made to support a generic design for the majority of users.

 

The engineers working on the IBERT designers have a tough job trying to satisfy a wide range of options for the MGTs and this means that they a large number of clocking resources are used leaving little to none left in the device.

 

A single-application design doesn't have the same set of constraints allowing the designer to be able to optimize the resources more effectively.  

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Observer mutaal
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2,374 Views
Registered: ‎05-14-2014

Re: proper procedure for testing a pair of GTP tranceivers

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Hi, 

 

I am using simular setup to run GTX Pcie_gen1 protocl using SATA crossover cables on ML507. Is that setup possible?

 

I am using SATA crossover cable. Is there any setting that need to done to use SATA in loop back mode ? Currently I don't see the SYNC state being changed. That is what I saw on chip scope. 

 

Any help would be highly regarded.

 

Thanks

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