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xilinx jesd204b core's SYNC and SYSREF

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Posts: 5
Registered: ‎06-06-2018

xilinx jesd204b core's SYNC and SYSREF

Hello,

 

I am trying to interface Xilinx FPGA xc7k70tfbg676-1 to the AD9172 DAC. I have developed a basic block design just to test the JESD204B interface. I am using Xilinx JESD204B IP core v5.2. I am trying to map the sysref and sync signal inputs to the FMC connector pins and Vivado pops up with an error "Cannot place GT terminals on non GT pins. According to the datasheet of mentioned fpga, it has two GTX banks i.e. 115 and 116 and sysref and sync are to be mapped on this I/O banks according to the schematic of AD9172 board. The schematic of AD9172 board says that I have to map the SYNC0 output from DAC to the G17 and F18 pins on the FPGA which I am not able to do it because of the above mentioned error. G17 and F18 pins are present on the bank 15 which is not a GTX bank. Any help will be appreciated. 

 

Regards,

 

Loukik Pingle

 

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