02-08-2019 04:25 PM
Do you have the Xilinx tools installed? That might be a good first step... https://www.xilinx.com/support/download.html
Also, some forum basics... https://forums.xilinx.com/t5/custom/page/page-id/community_guidelines
Hope that helps
If so, please mark solution accepted. Kudos also welcomed. :-)
02-08-2019 05:02 PM - edited 02-08-2019 05:06 PM
Welcome to the Xilinx Forum!
If you are very familiar with the Altera Quartus tools then your transition to the Xilinx tools will not be too painful.
For most of the new FPGAs, you will need to use the tools called Vivado. Table 2-1 of UG973 shows the FPGAs supported by Vivado. You will note from Table 2-1 that there is a free-of-charge version of Vivado called “WebPACK Vivado” which supports only some of the newer FPGAs. Both the free and not-free versions of Vivado can be downloaded from <here>.
The “flow” of the Xilinx tools is like the Quartus tool: 1) write code (eg. VHDL or Verilog), 2) add code Xilinx wrote for you (called Intellectual Property (IP) modules), 3) write Tcl constraints, 4) simulate (if you want), 5) click on synthesis, 6) click on implementation, 7) check timing analysis, 8) generate bitstream, 9) send bitstream to the FPGA.
You’ll find tutorials and learning videos on the Xilinx website to help you learn ISE and Vivado.
What Xilinx FPGA will you be working with?