How to set the AXI Memory Map Slave Port in RTL Kernel Wizard?
I have a question about the AXI Memory Map Slave Port. Now I am using SDAccel 2018.3 RTL Kernel Wizard to wrap an RTL Kernel. My top module of RTL Kernel has three kinds of ports, AXI_Lite(Control), AXI_MM(Memory Map) and one AXI_MM slave port for DMA/Bridge Subsystem for PCI Express.
I know how to handle the first two types of port by setting their parameter in the Gerenal setting of RTL Kernel Wizard. However, I don't know how to handle the AXI_MM slave port. It can't be set as scalar port, it also cannot be set in the Global memory, because Global memory setting only care the master port, but the AXI_MM for DMA/Bridge Subsystem for PCIe is a slave port. Can someone tell me, how should I handle this port?