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Registered: ‎04-15-2019

Internal loopback on ethernet_lite bitstream generation problem

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Hello eveyone!

My aim is to configure ethernet_lite IP in Artix board in internal loopback.

For that, I made the following block diagram in Vivado.
BlockDiagram-Ethernet_liteBlockDiagram-Ethernet_liteThis Block Diagram is getting successfully implemented. I am constraining the ethernet_lite IP same as the user guide of AC701 provided by Xilinx.

 

UG952_Ethernet_ConstraintsUG952_Ethernet_Constraints

After clicking on "Generate Bitstream", I am getting the following error.

Bitstream_ErrorBitstream_Error

NOTE: I unplaced the pins (Ctrl+U) in I/O ports window  because the ports: mii_rtl_col, mii_rtl_crs are required in half duplex but I'm using full duplex.

Other ports such as mii_rtl_er, mii_rtl_dv I have unplaced because they were mentioned nowhere in UG952. Also, I have given the following constraints.

-------------------------------Constraints------------------------------------------

set_property IOSTANDARD LVCMOS18 [get_ports {mii_rtl_rxd[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports {mii_rtl_rxd[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {mii_rtl_rxd[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {mii_rtl_rxd[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {mii_rtl_txd[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports {mii_rtl_txd[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {mii_rtl_txd[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {mii_rtl_txd[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports mii_rtl_crs]
set_property PACKAGE_PIN U21 [get_ports mii_rtl_rx_clk]
set_property IOSTANDARD LVCMOS18 [get_ports mii_rtl_rx_clk]
set_property PACKAGE_PIN U22 [get_ports mii_rtl_tx_clk]
set_property IOSTANDARD LVCMOS18 [get_ports mii_rtl_tx_clk]
set_property PACKAGE_PIN T17 [get_ports {mii_rtl_txd[3]}]
set_property PACKAGE_PIN T18 [get_ports {mii_rtl_txd[2]}]
set_property PACKAGE_PIN U15 [get_ports {mii_rtl_txd[1]}]
set_property PACKAGE_PIN U16 [get_ports {mii_rtl_txd[0]}]
set_property PACKAGE_PIN V14 [get_ports {mii_rtl_rxd[3]}]
set_property PACKAGE_PIN V16 [get_ports {mii_rtl_rxd[2]}]
set_property PACKAGE_PIN V17 [get_ports {mii_rtl_rxd[1]}]
set_property PACKAGE_PIN U17 [get_ports {mii_rtl_rxd[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports mii_rtl_rst_n]
set_property PACKAGE_PIN V18 [get_ports mii_rtl_rst_n]

set_property PACKAGE_PIN T15 [get_ports mii_rtl_tx_en]
set_property IOSTANDARD LVCMOS18 [get_ports mii_rtl_tx_en]

set_property IOSTANDARD LVCMOS33 [get_ports {led_4bits_tri_o[2]}]

set_property IOSTANDARD LVCMOS18 [get_ports mii_rtl_rx_dv]
set_property IOSTANDARD LVCMOS18 [get_ports mii_rtl_rx_er]
set_property IOSTANDARD LVCMOS18 [get_ports mii_rtl_col]

---------------------------------------------------------End of constraints--------------------------------------

Please let me know regarding the proper constarints that are needed to be put in order to get this working.

Thanks!

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Scholar
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Registered: ‎08-07-2014

@aditya.725,

Do you know how to create a wrapper/top-level module for any module in RTL?

If yes, your job is done. In the wrapper/top-module just have the connectivity with the signals you want at the IO level.

Or you work only with block-design and don't care how RTL works?

In that case can't you just disconnect the the port from the signal? If you right-click on the not-needed signal and there will be an option, I am forgetting....

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Registered: ‎08-07-2014

@aditya.725 

Error message not properly visible with the screenshots. Please copy and post them properly.

Still figuring out....

If you are bringing those signals at the FPGA I/O level, then you MUST assign pins to them. I fyou don't need them just don't bring them out.

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Registered: ‎04-15-2019

@dpaul24 

The error that was shown in Vivado :-

------------------------------------------------------------------------------------------------------------------------

Pin planning

[DRC UCIO-1] Unconstrained Logical Port: 3 out of 145 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: mii_rtl_crs, mii_rtl_rx_dv, and mii_rtl_rx_er.

--------------------------------------------------------------------------------------------------------------------------

I guess I don't know the proper way to remove the unnecessary signals from the I/O ports. It'll be kind if you tell a way to remove the signals. Also, please let me know the solution regarding the situation where I need to configure the ports (as shown in error message of Vivado) that are not memtioned in datasheet.

Thanks!

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Registered: ‎08-07-2014

@aditya.725,

Do you know how to create a wrapper/top-level module for any module in RTL?

If yes, your job is done. In the wrapper/top-module just have the connectivity with the signals you want at the IO level.

Or you work only with block-design and don't care how RTL works?

In that case can't you just disconnect the the port from the signal? If you right-click on the not-needed signal and there will be an option, I am forgetting....

------------FPGA enthusiast------------
Consider giving "Kudos" if you like my answer. Please mark my post "Accept as solution" if my answer has solved your problem

View solution in original post

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Registered: ‎04-15-2019

@dpaul24 

You have been of great help. I understood by your top level wrapper statement that in VHDL coding, I need to remove the insignificant signals. I did that and guess what... Bitstream is successfully generated. :)

Now I need to see the polled mode example in ".mss" file of ethernet_lite IP example. If I get stuck anywhere, I hope you'll help me.

 

Sincere Gratitude!

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Registered: ‎08-07-2014

@aditya.725, most welcome!

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Registered: ‎04-15-2019

@dpaul24,

I imported the example "xemaclite_polled_example" from system.mss file as described below.

 

img1img1

 

img2img2

Now, the problem is that I am not able to loopback the frames properly (transmission ok and reception not ok).

In code, I made some changes such as reducing the delays explicitly and reducing the runtime of loops. The frames are getting transmitted but not getting received.

Where should the correction be made? I hope the hardware configurations made in Vivado are correct!!!

P.S. I am attaching the code for your reference.

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Registered: ‎04-15-2019

@dpaul24 

Kindly enlighten me with the solution.

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Registered: ‎08-07-2014

@aditya.725,

Please understand that I don't have enough time to go through entire projects and debugging code.

Now, the problem is that I am not able to loopback the frames properly (transmission ok and reception not ok).

A solution can only be given when the problem is known. Some tips for debugging...

1. How do you know that Tx is ok but not Rx?

2. Have an ILA core connected to the MAC transmit side (PHY interface side) and monitor the Ethernet frame pattern.

3. Connect your development board to a PC and run Wireshark on that network card. If your design is transmitting GOOD/LEGAL frames then Wireshark would capture them.

4. If <3> is good the monitor your Rx side with ILA core.

Nevertheless find out and read some old posts of the https://forums.xilinx.com/t5/Networking-and-Connectivity/bd-p/CONN sub-forum as to how people have done some debugging with Ethernet cores.

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