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Registered: ‎08-08-2019

Virtex-7 FPGAs source-synchronous-interface IDELAY


I'm currently a student working on a research project. I'm having a few questions regarding the Virtex-7 FPGAs, and really appreciated if I could find solution from this forum.


I am working on designing a customized ADC Eval-Board that can interface with Xilinx FPGA Board for DSP via FMC connectors. Meanwhile, we are also trying to decide which FPGA board we will eventually use.  


1. The ADC chips we are trying to design with (AD9267 from Analog Devices) is outputing LVDS signals. I wish to ask that what is the recommended data rate of LVDS from Xilinx? I couldn't find this information from the Virtex-7 datasheets. Could anyone help to point me where could I find this information? 

2. The outputs from the ADC chips are in single data rate (SDR) format. In order to sample the received data, I (think) will need to use the IDELAY feature to delay and line-up the data (if necessary). I wish to ask that what is the range of IDELAY that I can tune to compensate for all the process corners from my ADC_EVB board layout? What is the name of such parameter in the datasheet? 

Thank you very much for your time and helps! 




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Registered: ‎01-22-2015

The parameter for tuning IDELAY is IDELAY_VALUE shown in Table 2-5 of UG471(v1.10).  It has 32 values, each value representing a step/resolution, T(IDELAYRESOLUTION) = 1/(32 x 2 x FREF) us, as shown in Table 28 of DS183(v1.28).  The parameter, FREF, is the Reference Clock frequency described on page-124 of UG471.

I don’t think you’ll find a Xilinx recommended data-rate for LVDS, since other things inside the FPGA (eg. FMAX of BUFG or PLL) will limit data-rate before LVDS.


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