08-12-2019 04:19 AM
I am facing some problem when I am going to do bitstream generation. I am facing some error related .xdc file. My aim is to store the sinewave in FPGA (ZC706). My sine wave is 16 bit. but I connect the first four-bit to the LEDs(As there are only 4 GPIO LEDs) to check up the status. But unfortunately, I am facing the clk and others issue I mentioned in the attachment report. Please tell me how I can store the sinewave in FPGA? I am facing the XDC file issues. Is there any wrong in my writing of XDC file? I am using Vivado 2018.3 tools. Thanks in advance.
XDC file written by me
08-12-2019 04:38 AM
Sorry I can only just about read the snapshot of the error report on this machine,
By the looks of things, I'm guessing you have not specified all the pins the deisign uses,
something about 12 of 16 pins un defined / standard IO .
how are you generating this file ?
in vivado its not as easy as ISE, but ....
So assuming your design ha spassed simulaoitn is the first step,
If no t, do not proceed any further till it does.
Assuming you have selected the correct chip and package in your desing source,
You have tools under "open synthesised design"
constraints wizard is a good start, that gets your basic timming constraints set up with minimal fuss.
Now for a first pass open synthesised desing, and go to the top menu where you have tools, the IOPlanning, and go to auto place all ports.
This will give yo uth ebasic XDC file you can edit easily to move your pins to where you want, and gives you a starting place that you cna go back to that works,
08-12-2019 05:39 AM
Yes, I did not specify all the bit. As sinewave output is 16 bit, I just connect it with 4 GPIO LEDs which is only available LEDs. The left bit where should I connect? I am confused. Please suggest to me.
Secondly, there are no XDC file is generated after auto place all ports. Is anything wrong I am doing? I am following the document attached below. In this document, they list XDC constraints (page - 92).
08-12-2019 06:09 AM
08-12-2019 06:30 AM
If you want to create a 16-bit output but only use 4-output pins, you'll need to create a 4-bit output containing those four values rather than a 16-bit output bus of which only 4 are used.
08-12-2019 06:33 AM
I dont have vivaod to hand , but have a search around in the manual, its in there some where how to alocate pins,
08-12-2019 06:35 AM
Th ecode you write, has a number of Io pins in it
in the entity in VHDL.
The FPGA tools need ot knwo where each and every on eof these needs to be placed on the chip,
thats up to you, and your board.
A normal way to do this if you have a previously working desing , like a ref design is to modify the constraints file that comes with the board,