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Registered: ‎09-25-2014

sine wave generation issues

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Hi all, 

I am going to generate the sinewave in vivado tools. When I simulated the this gives the waveform like this below attachment. It is not showing the exact sine wave. Can you tell me where is my problem?? Thanks in advance.

regards,

Amitava11.PNG

 

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Teacher
Teacher
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Registered: ‎07-09-2009

Sorry , I dont think I cna help you any more on this,

 

We have pointedyou at the built in core fomr Xilxin, and the documentation ,

     we have pointed you at alternatives ,

 

All these seem to answer you questoin on how to generate your sine wave,

     If you have different quesoins, please mark this as completed, and start a new question with a specific problem.

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

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Scholar
Scholar
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Registered: ‎05-21-2015

middyaamitava@gmail.com,

Without any more information, the bug could be anything.

My first prejudiced guess, though, is that you tried to use radians and messed up the conversions within the FPGA.  Better not to use radians at all.

Dan

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Teacher
Teacher
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Registered: ‎07-09-2009
would be good to see your code,
out of interest, xilinx have a great IP , the DDS core, that does this very efficiently
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Registered: ‎09-25-2014

Hi Sir, 

After creating a new Testbench in Vivado, I wrote the Verilog source file. The easiest and fastest one is using an online sine generation tool. I generate the value from Sine Look Up Table Generator Calculator. After that, I stored the value in text file(sine.mem) and read them from a memory text file. I followed this link given below.

https://miscircuitos.com/sinus-wave-generation-with-verilog-using-vivado-for-a-fpga/?fbclid=IwAR3ZuwseXifxMG37dHR365FKevR47xWzmbp1Bu1EoUsXJ4I7R3hSGdcXL-s

The code was used is given below. 

module sinus_gen(
input clk ,
output reg [15:0] sinus
);
parameter SIZE = 1024;
reg [15:0] rom_memory [SIZE-1:0];
integer i;
initial begin
$readmemh("sine.mem", rom_memory);
i = 0;
end


//At every positive edge of the clock, output a sine wave sample.

always@(posedge clk)
begin
sinus = rom_memory[i];
i = i+ 1;
if(i == SIZE)
i = 0;
endendmodule

 

Another thing is how I can I use the DDS IP for sine wave generation? As I am new in this field, so please help. Actually, my aim is to store the sine wave in FPGA (ZC706). 

thanks,

Amitava11.PNG

 

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Teacher
Teacher
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Registered: ‎07-09-2009
As to how to use the dds IP tool,
There is extensive documentation on the Xilinx web site, just do a search, "xilinx dds"

Have you used other IP from Xilinx ?
its just the same way to instantiate the DDS IP.


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Registered: ‎09-25-2014

Ok, Sir. Thank you. But I am facing some problem when I am going to do bitstream generation. I am facing some error related .xdc file. My sine wave is 16 bit. but I connect the first four-bit to the LEDs(As there are only 4 GPIO LEDs) to check up the status. But unfortunately, I am facing the clk and others issue I mentioned in the attachment report.  Please tell me how I can store the sinewave in FPGA? I am facing the XDC file issues. Is there any wrong in my writing of XDC file? Please help me. Thanks in advance.

Thanks,

Amitava

11.PNG

                                               

Writing of XDC file

111.PNG

 

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Scholar
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Registered: ‎05-21-2015

middyaamitava@gmail.com,

Your problem is that you have two constraints on the same clk pin, each assigning it to different FPGA pins--one to pin H9 and one to pin G9.

Did you ever manage to fix your original sinewave generation issue?  If not, may I recommend you double check the number of values in your table?

Dan

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Registered: ‎09-25-2014

Hi Dan, 

when I  give the only one clock it showing error like"  I/O port clk is Single-Ended but has an IOStandard of LVDS which can only support Differential" So which pin number I should give? What you think.  I am using Vivado 2018.3 tools. 

 


 11.PNG

 

For the case of sine wave, I generate it from the online link Sine Look Up Table Generator Calculator.  https://daycounter.com/Calculators/Sine-Generator-Calculator.phtml.

I just copy from them. 
when I saw only behavioral simulation it is showing the correct sinewave. But when I run the Post synthesis functional simulation / Post implementation functional simulation, it's showing the same I posted before. Giving little distortion. 

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Teacher
Teacher
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Registered: ‎07-09-2009

you might also be interested in these great guys

 

https://www.doulos.com/knowhow/vhdl_designers_guide/models/sine_wave_generator/

 

 

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Registered: ‎09-25-2014

Ok. But I have to store sinewave in FPGA. I have mentioned that in the previous post.  How I can solve the constraints issues? Please help me. As I am very new in this area. 

thanks,

Amitava

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Teacher
Teacher
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Registered: ‎07-09-2009

Sorry , I dont think I cna help you any more on this,

 

We have pointedyou at the built in core fomr Xilxin, and the documentation ,

     we have pointed you at alternatives ,

 

All these seem to answer you questoin on how to generate your sine wave,

     If you have different quesoins, please mark this as completed, and start a new question with a specific problem.

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

View solution in original post

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