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Visitor
Visitor
494 Views
Registered: ‎08-15-2019

timing closure

i'm working with a vivado project. I baselined the project and the timing is met. Then i added I/O constraints to it and after synthesis there are some timing violations:

2019-08-18_123816.pngI opend the detail information about path 1:

2019-08-18_123843.pngand the relative schematic is:

2019-08-18_123905.png

i think the clock path skew and OBUF delay are too big, but i don't know how to handle this.

can you give me some sugesstions?

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Teacher
Teacher
468 Views
Registered: ‎07-09-2009

If you can add an extra output register, problem solved,
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Visitor
Visitor
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Registered: ‎08-15-2019

It works. Thank you very much !  

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Visitor
Visitor
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Registered: ‎08-15-2019

The method you provided solved sevel paths, but there ara still some paths failed to meet timing:

path1.pngschematic.pngsum.png

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Teacher
Teacher
431 Views
Registered: ‎07-09-2009

looks like you bring the clock into the fpga, and then just buffer.

 

The FPGAs have a compoenet to instantiate, the clock buffer, probable a mmcm in your chip.

 

This you feed the external clock into , and the output becomes your on chip clock,

    the advantage is the DLL in in the MMCM, removes the effective delay of the input buffers,

 

You timing constrain just the same, just to the clock in pin , the s/w then generates its own internal timming constraints for you

 

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Visitor
Visitor
424 Views
Registered: ‎08-15-2019

Hi, I instantiate a MMCM block, the violation decressed but still cannot meet the timing:

path1_2.pngsum2.png

the clock skew is really large, is it ok?

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418 Views
Registered: ‎07-23-2019

@vinson888 

There isn't a single recipe to fix timing closure, the whole thing has to be analyzed. Attaching the results doesn't help. Could you share at least your constraints?

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Visitor
Visitor
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Registered: ‎08-15-2019

the constraints is as follows:

set_input_delay -clock [get_clocks clk_out1_clk_wiz_0] -min 0.1 [get_ports {recword[*]}]
set_input_delay -clock [get_clocks clk_out1_clk_wiz_0] -max 0.2 [get_ports {recword[*]}]

set_input_delay -clock [get_clocks clk_out1_clk_wiz_0] 0.2 [get_ports reset]
set_input_delay -clock [get_clocks clk_out1_clk_wiz_0] 0.2 [get_ports start]

set_output_delay -clock [get_clocks clk_out1_clk_wiz_0] -min -0.1 [get_ports {corr_recword[*]}]
set_output_delay -clock [get_clocks clk_out1_clk_wiz_0] -max 0.2 [get_ports {corr_recword[*]}]

set_output_delay -clock [get_clocks clk_out1_clk_wiz_0] -min -0.1 [get_ports dataoutend]
set_output_delay -clock [get_clocks clk_out1_clk_wiz_0] -max 0.2 [get_ports dataoutend]

set_output_delay -clock [get_clocks clk_out1_clk_wiz_0] -min -0.1 [get_ports dataoutstart]
set_output_delay -clock [get_clocks clk_out1_clk_wiz_0] -max 0.2 [get_ports dataoutstart]

set_output_delay -clock [get_clocks clk_out1_clk_wiz_0] -min -0.1 [get_ports decode_fail]
set_output_delay -clock [get_clocks clk_out1_clk_wiz_0] -max 0.2 [get_ports decode_fail]

set_output_delay -clock [get_clocks clk_out1_clk_wiz_0] -min -0.1 [get_ports errfound]
set_output_delay -clock [get_clocks clk_out1_clk_wiz_0] -max 0.2 [get_ports errfound]

set_output_delay -clock [get_clocks clk_out1_clk_wiz_0] -min -0.1 [get_ports ready]
set_output_delay -clock [get_clocks clk_out1_clk_wiz_0] -max 0.2 [get_ports ready]

and the relative 2 files targed.

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407 Views
Registered: ‎07-23-2019

@vinson888 

You need to add a create_clock for your clocks. Why not giving the wizard a go?

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Visitor
Visitor
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Registered: ‎08-15-2019

The IP created the clock constraint automatically, need i cover it ?

constraints.png

i tried, but it dosen't help.

 

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Teacher
Teacher
390 Views
Registered: ‎07-09-2009

you now need to look at the timming results, see where th elong paths are,

then look at your verilog code, and work out how to make those paths faster in you rcode.

Hint : Pipe lining,

 

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Registered: ‎07-23-2019

@vinson888 

If the constraint is there it's fine, no need to duplicate.

Now the question is if your period is 20 ns, why do you need to constrain your data so tightly? 

Also, you may not want your data changing before your clock. If your output data changes -0.1 ns before the clock comes out, the thing receiving your output will capture the result in the same clock and that requires the clock to be delayed. Normally, data is delayed respect to the clock and the next clock captures the result. 

Try min delay +1 ns, max 15 ns. 

 

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Visitor
Visitor
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Registered: ‎08-15-2019

Actually I've pipelined the path!

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Visitor
Visitor
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Registered: ‎08-15-2019

The MMCM's input clock's frequency is 50MHz , the output clock's is 250MHz, and my design works on 250MHz.  

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377 Views
Registered: ‎07-23-2019

@vinson888 

Do you have a testbench? create one, think of your inputs and the outputs you expect and simulate. Timing is tricky, is probably the essential difference between processors and FPGA. In a processor things are perfectly synchronized, Everything that can be done in a clock period is done and dusted in that time. With FPGA is different, every signal path has to be checked.

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Registered: ‎07-23-2019

@vinson888 

okay... in that case you need a constraint for your output clock with 4 ns period. Even though, you could spec your outputs with, say, +0.5 and 3.5 ns

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Visitor
Visitor
361 Views
Registered: ‎08-15-2019

I changed the constraints as follows: 

constr.png\

3.5 is too big i think, so i make it 1.5  but the violation incressed.

sum.png

dose the main factor that cause the violation is clock skew( it is -1.096ns ) ?  

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Registered: ‎07-23-2019

 

These errors are intra-clock paths, nothing to do with output delay constraints.

If you cannot meet the setup (again without having a detailed look at your design, it takes time...) is probably because the combinatorial stuff you have between registers takes too long. 

 

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354 Views
Registered: ‎07-23-2019

do you have products in there?

Even 8-bit int multiplications may take longer than 4 ns. In that case, you should constrain them as a multicycle path. 

Timing simulations of the synthesized design (not the behavioural) will show you everything

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Teacher
Teacher
340 Views
Registered: ‎07-09-2009

My fault, i assumed you had the clock constrained orriginaly,

 

id take a step back,

take off your IO constraints,

Just have the clock constraint,

   fist you need to get your design working with that clock constraint,

       I'd also suggets you constrain th elcok in your XDC file.

 

I know its constrained in the MMCM IP,

     but if you put the constriant in your XDC, then its obvious and clear, and it over writes the one in the IP.

 

Once you have the closked desing working, then look at the Io ocnstraints,

    BTW: at that time, you alos need to constrain the IO as to type, and voltage.

 

BUT ONLY after you have the deisng passing timming with no IO constraints.

https://www.xilinx.com/content/dam/xilinx/support/documentation/sw_manuals/xilinx2019_1/ug949-vivado-design-methodology.pdf?bcsi_scan_76a858e05751204b=0&bcsi_scan_filename=ug949-vivado-design-methodology.pdf

https://www.xilinx.com/video/hardware/using-vivado-timing-constraint-wizard.html

https://www.xilinx.com/support/documentation-navigation/design-hubs/dh0006-vivado-design-analysis-and-timing-closure-hub.html

 

 

 

 

 

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Guide
Guide
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Registered: ‎01-23-2009

The things others have suggested are steps along the right path

  • Use a flip-flop on the output
    • Ensure that this is packed into the IOB (using the IOB property)
      • This may not have been mentioned
  • Use an MMCM to remove the clock insertion delay

But let't take a step back - what do you need.

Your constraints are currently specified with respect to the clock output of the MMCM - that is "unusual" (aka "wrong"). The set_output_delay command is used to tell the tools what the requirement of the system are - the system doesn't have access to the internal node of the design that carries the clock output of the MMCM - therefore the system can't possibly need a specific requirement with respect to this point. So what is the requirement?

Tell us about the system topology. What device is being driven by this output port? What is the clock that this device uses? Specifically is this a system synchronous interface (the FPGA and the device share the same board clock) or a source synchronous interface (the FPGA forwards a clock to the device). In the former case, the timing requirements (set_output_delay) would be specified with respect to the input clock of the FPGA (not the MMCM clock). In the latter case, the set_output_delay would be specified with respect to the forwarded clock (using a create_generated_clock command) - assuming the forwarded clock is generated properly (using an IDDR). In neither case would the output clock of the MMCM be used...

Avrum

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Visitor
Visitor
310 Views
Registered: ‎08-15-2019

Hi, actually my design is a  reed-solomon decoder which is going to work in the physical layer.

The module behind my rsdecoder is Convolutional decoder. Both these two decoder are submodule of physical module so i think my design(RSDecoder) need not to drive any block. Does this mean there needn't "set_output_delay"? 

There is a OSC on the fpga board whose frequency is 50MHz and my design is going to work on 250MHz.

And I am testing the design on the fpga board, there isn't any other device. So i think it is system synchronous.

 

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Teacher
Teacher
300 Views
Registered: ‎07-09-2009

input and output delays are only for signals on th eIo pins of the FPGA,

if you dont care about IO, then don't put IO delays on..

 

system synchronous is a new topic please

 

I assume you rusing the MMCM to multipy the 50 Mhz to 250 MHz,

 

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Guide
Guide
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Registered: ‎01-23-2009

I am not clear on what you are trying to do here...

It appears you are developing one module of a system in isolation. My understanding is that this module will be (ultimately) integrated into a design with other modules - this module will not communicate directly with anything outside the FPGA.

So what is your goal here?

  • prove that this module can meet timing at your desired frequency?
  • prove that it works functionally? Are you trying to do this by
    • Simulation?
    • Implementation and testing on a development board?
      • If so, how are you applying stimulus and examining/checking the response

The answer to these questions will better help us guide you. We have been assuming (up until this point) that this module needed to communicate with an external device that had specific timing requirements, and most of the recommendations we have been giving you have been toward solving this problem. If this is not the case, then most of what you have been told is probably not valid...

Avrum

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