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Observer
Observer
1,758 Views
Registered: ‎10-06-2018

Linux running on APU with two RPU slaves (2)

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I am aware of

https://forums.xilinx.com/t5/OpenAMP/Linux-running-on-APU-with-two-RPU-slaves/td-p/796915

and

https://forums.xilinx.com/t5/OpenAMP/Enclustra-XU1-run-2-RPU-slaves-at-the-same-time/td-p/918208

but they don't help with my problem.

I have two "hello world" applications for r5_0 and r5_1 which work fine when loaded via JTAG with SDK. However, I have no output from r5_1 when loaded with /sys/class/remoteproc/remoteproc1. r5_0 works fine.

The output in linux from remoteproc looks normal when loading r5_1, same as for r5_0.

All sections are in TCM, so memory conflicts can be ruled out ?

The device tree is pasted below, similar to UG1137, p. 245

/include/ "system-conf.dtsi"
/ {
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
rproc_0_reserved: rproc@70000000 {
no-map;
reg = <0x0 0x70000000 0x0 0x10000000>;
};
};

amba {
/* Shared memory */
shm0: shm@78000000 {
compatible = "shm_uio";
reg = <0x0 0x78000000 0x0 0x8000000>;
};
/* IPI device */
ipi_amp: ipi@ff340000 {
compatible = "ipi_uio";
reg = <0x0 0xff340000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 29 4>;
};

};

};


/ {
power-domains {
pd_r5_0: pd_r5_0 {
#power-domain-cells = <0x0>;
pd-id = <0x7>;
};
pd_r5_1: pd_r5_1 {
#power-domain-cells = <0x0>;
pd-id = <0x8>;
};
pd_tcm_0_a: pd_tcm_0_a {
#power-domain-cells = <0x0>;
pd-id = <0xf>;
};
pd_tcm_0_b: pd_tcm_0_b {
#power-domain-cells = <0x0>;
pd-id = <0x10>;
};
pd_tcm_1_a: pd_tcm_1_a {
#power-domain-cells = <0x0>;
pd-id = <0x11>;
};
pd_tcm_1_b: pd_tcm_1_b {
#power-domain-cells = <0x0>;
pd-id = <0x12>;
};
};
amba {
/* firmware memory nodes */
r5_0_tcm_a: tcm@ffe00000 {
compatible = "mmio-sram";
reg = <0x0 0xFFE00000 0x0 0x10000>;
pd-handle = <&pd_tcm_0_a>;
};
r5_0_tcm_b: tcm@ffe20000 {
compatible = "mmio-sram";
reg = <0x0 0xFFE20000 0x0 0x10000>;
pd-handle = <&pd_tcm_0_b>;
};
r5_1_tcm_a: tcm@ffe90000 {
compatible = "mmio-sram";
reg = <0x0 0xFFE90000 0x0 0x10000>;
pd-handle = <&pd_tcm_1_a>;
};
r5_1_tcm_b: tcm@ffeb0000 {
compatible = "mmio-sram";
reg = <0x0 0xFFEB0000 0x0 0x10000>;
pd-handle = <&pd_tcm_1_b>;
};
elf_ddr_0: ddr@70000000 {
compatible = "mmio-sram";
reg = <0x0 0x70000000 0x0 0x2000000>;
};
elf_ddr_1: ddr@72000000 {
compatible = "mmio-sram";
reg = <0x0 0x72000000 0x0 0x2000000>;
};
test_r5_0: zynqmp_r5_rproc@0 {
compatible = "xlnx,zynqmp-r5-remoteproc-1.0";
reg = <0x0 0xff9a0100 0x0 0x100>,
<0x0 0xff9a0000 0x0 0x100>;
reg-names = "rpu_base", "rpu_glbl_base";
dma-ranges;
core_conf = "split0";
srams = <&r5_0_tcm_a &r5_0_tcm_b &elf_ddr_0>;
pd-handle = <&pd_r5_0>;
};
test_r5_1: zynqmp_r5_rproc@1 {
compatible = "xlnx,zynqmp-r5-remoteproc-1.0";
reg = <0x0 0xff9a0200 0x0 0x100>,
<0x0 0xff9a0000 0x0 0x100>;
reg-names = "rpu_base", "rpu_glbl_base";
dma-ranges;
core_conf = "split1";
srams = <&r5_1_tcm_a &r5_1_tcm_b &elf_ddr_1>;
pd-handle = <&pd_r5_1>;
};
};

};

&uart1 {
status = "disabled";
};

&ttc2 {
status = "disabled";
};

 

 

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Observer
Observer
1,601 Views
Registered: ‎10-06-2018

I found that bit 0 of RPU1_CFG , addr 0xff9a0200, is cleared which means that the CPU is halted.

I am able to start r5_1 by setting this bit.

Therefore, a workaround is

a) load and start r5_1 with remoteproc

b) load and start r5_0 with remoteproc

r5_0 sets the bit 0 of RPU1_CFG to start r5_1.

Question remaining is why is it not done by remoteproc ?

View solution in original post

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Moderator
Moderator
1,693 Views
Registered: ‎05-10-2017

Which version of the tools are you using? Could you please provide your console log? Is RPMsg in userspace or kernel space?

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Observer
Observer
1,686 Views
Registered: ‎10-06-2018

using version 2018.3 for all tools

root@xilinx-zcu104-2018_3:~# echo hello_r5_0.elf > /sys/class/remoteproc/remoteproc0/firmware 
root@xilinx-zcu104-2018_3:~# echo start > /sys/class/remoteproc/remoteproc0/state                                                             
[  120.932954] remoteproc remoteproc0: powering up ff9a0100.zynqmp_r5_rproc
[  120.940112] remoteproc remoteproc0: Booting fw image hello_r5_0.elf, size 222756
[  120.947565] zynqmp_r5_remoteproc ff9a0100.zynqmp_r5_rproc: RPU boot from TCM.
[  120.955271] remoteproc remoteproc0: remote processor ff9a0100.zynqmp_r5_rproc is now up

printing "hello world from r5_0" to other UART

root@xilinx-zcu104-2018_3:~# echo hello_r5_1.elf > /sys/class/remoteproc/remoteproc1/firmware                                                         
root@xilinx-zcu104-2018_3:~# echo start > /sys/class/remoteproc/remoteproc1/state                                                                     
[  159.452936] remoteproc remoteproc1: powering up ff9a0200.zynqmp_r5_rproc
[  159.460113] remoteproc remoteproc1: Booting fw image hello_r5_1.elf, size 232976
[  159.467582] zynqmp_r5_remoteproc ff9a0200.zynqmp_r5_rproc: RPU boot from TCM.
[  159.475243] remoteproc remoteproc1: remote processor ff9a0200.zynqmp_r5_rproc is now up
root@xilinx-zcu104-2018_3:~# 

no output from r5_1

RPMsg is not involved, just using remoteproc

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Moderator
Moderator
1,684 Views
Registered: ‎05-10-2017

If you are not using rpmsg, the shm and ipi_amp nodes are not needed. Is your rpu-firmware installed under /lib/firmware?

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Observer
Observer
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Registered: ‎10-06-2018

The shm and ipi_amp nodes will be needed for my application. Because this doesn't run on the 2nd r5 core, I reverted to "hello world" examples to keep it as simple as possible. Can the shm and ipi_amp nodes prevent the "hello world" app running on the 2nd r5 ? Shall I remove them ?

Yes, the elf files are in /lib/firmware

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Moderator
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Registered: ‎05-10-2017

Try it without adding the shm and ipi nodes. I just ran this on a ZCU102. I just removed the ipi and shm nodes from the device-tree that you shared

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Observer
Observer
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Registered: ‎10-06-2018

same result

new device tree below

/include/ "system-conf.dtsi"
/ {
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
rproc_0_reserved: rproc@70000000 {
no-map;
reg = <0x0 0x70000000 0x0 0x10000000>;
};
};


};

/ {
power-domains {
pd_r5_0: pd_r5_0 {
#power-domain-cells = <0x0>;
pd-id = <0x7>;
};
pd_r5_1: pd_r5_1 {
#power-domain-cells = <0x0>;
pd-id = <0x8>;
};
pd_tcm_0_a: pd_tcm_0_a {
#power-domain-cells = <0x0>;
pd-id = <0xf>;
};
pd_tcm_0_b: pd_tcm_0_b {
#power-domain-cells = <0x0>;
pd-id = <0x10>;
};
pd_tcm_1_a: pd_tcm_1_a {
#power-domain-cells = <0x0>;
pd-id = <0x11>;
};
pd_tcm_1_b: pd_tcm_1_b {
#power-domain-cells = <0x0>;
pd-id = <0x12>;
};
};
amba {
/* firmware memory nodes */
r5_0_tcm_a: tcm@ffe00000 {
compatible = "mmio-sram";
reg = <0x0 0xFFE00000 0x0 0x10000>;
pd-handle = <&pd_tcm_0_a>;
};
r5_0_tcm_b: tcm@ffe20000 {
compatible = "mmio-sram";
reg = <0x0 0xFFE20000 0x0 0x10000>;
pd-handle = <&pd_tcm_0_b>;
};
r5_1_tcm_a: tcm@ffe90000 {
compatible = "mmio-sram";
reg = <0x0 0xFFE90000 0x0 0x10000>;
pd-handle = <&pd_tcm_1_a>;
};
r5_1_tcm_b: tcm@ffeb0000 {
compatible = "mmio-sram";
reg = <0x0 0xFFEB0000 0x0 0x10000>;
pd-handle = <&pd_tcm_1_b>;
};
elf_ddr_0: ddr@70000000 {
compatible = "mmio-sram";
reg = <0x0 0x70000000 0x0 0x2000000>;
};
elf_ddr_1: ddr@72000000 {
compatible = "mmio-sram";
reg = <0x0 0x72000000 0x0 0x2000000>;
};
test_r5_0: zynqmp_r5_rproc@0 {
compatible = "xlnx,zynqmp-r5-remoteproc-1.0";
reg = <0x0 0xff9a0100 0x0 0x100>,
<0x0 0xff9a0000 0x0 0x100>;
reg-names = "rpu_base", "rpu_glbl_base";
dma-ranges;
core_conf = "split0";
srams = <&r5_0_tcm_a &r5_0_tcm_b &elf_ddr_0>;
pd-handle = <&pd_r5_0>;
};
test_r5_1: zynqmp_r5_rproc@1 {
compatible = "xlnx,zynqmp-r5-remoteproc-1.0";
reg = <0x0 0xff9a0200 0x0 0x100>,
<0x0 0xff9a0000 0x0 0x100>;
reg-names = "rpu_base", "rpu_glbl_base";
dma-ranges;
core_conf = "split1";
srams = <&r5_1_tcm_a &r5_1_tcm_b &elf_ddr_1>;
pd-handle = <&pd_r5_1>;
};
};

};

&uart1 {
status = "disabled";
};

&ttc2 {
status = "disabled";
};
root@xilinx-zcu104-2018_3:~# ls -l /sys/bus/platform/devices/
total 0
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 70000000.ddr -> ../../../devices/platform/amba/70000000.ddr
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 72000000.ddr -> ../../../devices/platform/amba/72000000.ddr
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 Fixed MDIO bus.0 -> ../../../devices/platform/Fixed MDIO bus.0
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 alarmtimer -> ../../../devices/platform/alarmtimer
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 amba -> ../../../devices/platform/amba
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 amba_apu@0 -> ../../../devices/platform/amba_apu@0
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 clk -> ../../../devices/platform/clk
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 cpu_opp_table -> ../../../devices/platform/cpu_opp_table
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 cpufreq-dt -> ../../../devices/platform/cpufreq-dt
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 edac -> ../../../devices/platform/edac
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 fd070000.memory-controller -> ../../../devices/platform/amba/fd070000.memory-controller
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 fd0c0000.ahci -> ../../../devices/platform/amba/fd0c0000.ahci
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 fd400000.zynqmp_phy -> ../../../devices/platform/amba/fd400000.zynqmp_phy
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 fd4a0000.zynqmp-display -> ../../../devices/platform/amba/fd4a0000.zynqmp-display
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 fd4a0000.zynqmp-display:zynqmp_dp_snd_card -> ../../../devices/platform/amba/fd4a0000.zynqmpd
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 fd4a0000.zynqmp-display:zynqmp_dp_snd_codec0 -> ../../../devices/platform/amba/fd4a0000.zynq0
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 fd4a0000.zynqmp-display:zynqmp_dp_snd_pcm0 -> ../../../devices/platform/amba/fd4a0000.zynqmp0
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 fd4a0000.zynqmp-display:zynqmp_dp_snd_pcm1 -> ../../../devices/platform/amba/fd4a0000.zynqmp1
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 fd4b0000.gpu -> ../../../devices/platform/amba/fd4b0000.gpu
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 fd4c0000.dma -> ../../../devices/platform/amba/fd4c0000.dma
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 fd4d0000.watchdog -> ../../../devices/platform/amba/fd4d0000.watchdog
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 fd500000.dma -> ../../../devices/platform/amba/fd500000.dma
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 fd510000.dma -> ../../../devices/platform/amba/fd510000.dma
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 fd520000.dma -> ../../../devices/platform/amba/fd520000.dma
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 fd530000.dma -> ../../../devices/platform/amba/fd530000.dma
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 fd540000.dma -> ../../../devices/platform/amba/fd540000.dma
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 fd550000.dma -> ../../../devices/platform/amba/fd550000.dma
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 fd560000.dma -> ../../../devices/platform/amba/fd560000.dma
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 fd570000.dma -> ../../../devices/platform/amba/fd570000.dma
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 fd6e0000.cci -> ../../../devices/platform/amba/fd6e0000.cci
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 fd6e9000.pmu -> ../../../devices/platform/amba/fd6e0000.cci/fd6e9000.pmu
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 fe200000.dwc3 -> ../../../devices/platform/amba/ff9d0000.usb0/fe200000.dwc3
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 ff000000.serial -> ../../../devices/platform/amba/ff000000.serial
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 ff030000.i2c -> ../../../devices/platform/amba/ff030000.i2c
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 ff070000.can -> ../../../devices/platform/amba/ff070000.can
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 ff0a0000.gpio -> ../../../devices/platform/amba/ff0a0000.gpio
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 ff0e0000.ethernet -> ../../../devices/platform/amba/ff0e0000.ethernet
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 ff0f0000.spi -> ../../../devices/platform/amba/ff0f0000.spi
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 ff150000.watchdog -> ../../../devices/platform/amba/ff150000.watchdog
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 ff170000.mmc -> ../../../devices/platform/amba/ff170000.mmc
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 ff180000.pinctrl -> ../../../devices/platform/amba/ff180000.pinctrl
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 ff960000.memory-controller -> ../../../devices/platform/amba/ff960000.memory-controller
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 ff9905c0.mailbox -> ../../../devices/platform/ff9905c0.mailbox
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 ff9a0100.zynqmp_r5_rproc -> ../../../devices/platform/amba/ff9a0100.zynqmp_r5_rproc
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 ff9a0200.zynqmp_r5_rproc -> ../../../devices/platform/amba/ff9a0200.zynqmp_r5_rproc
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 ff9d0000.usb0 -> ../../../devices/platform/amba/ff9d0000.usb0
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 ffa00000.perf-monitor -> ../../../devices/platform/amba/ffa00000.perf-monitor
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 ffa50000.ams -> ../../../devices/platform/amba/ffa50000.ams
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 ffa60000.rtc -> ../../../devices/platform/amba/ffa60000.rtc
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 ffa80000.dma -> ../../../devices/platform/amba/ffa80000.dma
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 ffa90000.dma -> ../../../devices/platform/amba/ffa90000.dma
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 ffaa0000.dma -> ../../../devices/platform/amba/ffaa0000.dma
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 ffab0000.dma -> ../../../devices/platform/amba/ffab0000.dma
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 ffac0000.dma -> ../../../devices/platform/amba/ffac0000.dma
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 ffad0000.dma -> ../../../devices/platform/amba/ffad0000.dma
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 ffae0000.dma -> ../../../devices/platform/amba/ffae0000.dma
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 ffaf0000.dma -> ../../../devices/platform/amba/ffaf0000.dma
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 ffe00000.tcm -> ../../../devices/platform/amba/ffe00000.tcm
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 ffe20000.tcm -> ../../../devices/platform/amba/ffe20000.tcm
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 ffe90000.tcm -> ../../../devices/platform/amba/ffe90000.tcm
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 ffeb0000.tcm -> ../../../devices/platform/amba/ffeb0000.tcm
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 fpga-full -> ../../../devices/platform/fpga-full
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 nvmem_firmware -> ../../../devices/platform/nvmem_firmware
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 pcap -> ../../../devices/platform/pcap
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 pmu -> ../../../devices/platform/pmu
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 power-domains -> ../../../devices/platform/power-domains
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 psci -> ../../../devices/platform/psci
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 reg-dummy -> ../../../devices/platform/reg-dummy
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 regulatory.0 -> ../../../devices/platform/regulatory.0
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 reset-controller -> ../../../devices/platform/reset-controller
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 serial8250 -> ../../../devices/platform/serial8250
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 sha384 -> ../../../devices/platform/sha384
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 snd-soc-dummy -> ../../../devices/platform/snd-soc-dummy
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 timer -> ../../../devices/platform/timer
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 xhci-hcd.0.auto -> ../../../devices/platform/amba/ff9d0000.usb0/fe200000.dwc3/xhci-hcd.0.auto
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 xlnx-drm.0 -> ../../../devices/platform/amba/fd4a0000.zynqmp-display/xlnx-drm.0
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 zynqmp-power -> ../../../devices/platform/zynqmp-power
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 zynqmp_aes -> ../../../devices/platform/zynqmp_aes
lrwxrwxrwx    1 root     root             0 Jan 21 20:00 zynqmp_rsa -> ../../../devices/platform/zynqmp_rsa

 

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Moderator
Moderator
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Registered: ‎05-10-2017

You have modified your bsp settings for r5-1 output to appear on uart-1 right? Can you check if have the baud rate set to 115200

 

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Observer
Observer
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Registered: ‎10-06-2018

I am not doing any UART initialization in the hello world program. Because r5_0 can print to UART_1, I assume it has the correct settings by default and r5_1 should be able to print too.

I changed back to UART_0 to rule out any problem with UART_1, but the result is the same.

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Observer
Observer
1,614 Views
Registered: ‎10-06-2018

Added some test code in boot.S to toggle some pins,

/* this initializes the various processor modes */

_prestart:
_boot:



    ldr r0, =XPAR_MYIP_0_S00_AXI_BASEADDR
    ldr r1, =0x55555555
    str r1, [r0]

OKToRun:

/* Initialize processor registers to 0 */
	mov	r0,#0
	mov	r1,#0
	mov	r2,#0

In r5_0 the pins toggle as expected, nothing happens with r5_1, means the CPU never gets there. Seems the binary is not loaded correctly ?

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Observer
Observer
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Registered: ‎10-06-2018

I used the working processor r5_0 to print out the first words of all TCMs. The content is the same for r5_0 and r5_1.

Seems to me the reset for r5_1 is not released. How is the release of the reset controlled ?

#define r5_0_tcm_a 0xffe00000
#define r5_0_tcm_b 0xffe20000
#define r5_1_tcm_a 0xffe90000
#define r5_1_tcm_b 0xffeb0000

#define MAX 20


int main()
{
    init_platform();

    int i, addr;


    addr = r5_0_tcm_a;
    xil_printf("\r\nr5_0_tcm_a:\r\n");
    for(i=0; i < MAX; i++)
	{
	xil_printf("%x\r\n", *((int *)addr));
	addr +=4;
	}
    xil_printf("\r\n");

    addr = r5_0_tcm_b;
    xil_printf("r5_0_tcm_b:\r\n");
    for(i=0; i < MAX; i++)
	{
	xil_printf("%x\r\n", *((int *)addr));
	addr +=4;
	}
    xil_printf("\r\n");

    addr = r5_1_tcm_a;
    xil_printf("r5_1_tcm_a:\r\n");
    for(i=0; i < MAX; i++)
	{
	xil_printf("%x\r\n", *((int *)addr));
	addr +=4;
	}
    xil_printf("\r\n");

    addr = r5_1_tcm_b;
    xil_printf("r5_1_tcm_b:\r\n");
    for(i=0; i < MAX; i++)
	{
	xil_printf("%x\r\n", *((int *)addr));
	addr +=4;
	}
    xil_printf("\r\n");

 

r5_0_tcm_a:
E59FF018
E59FF018
E59FF018
E59FF018
E59FF018
E320F000
E59FF014
E59FF014
3C
1674
1690
16D0
16B4
162C
1664
E59F026C
E59F126C
E5801000
E3A00000
E3A01000

r5_0_tcm_b:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

r5_1_tcm_a:
E59FF018
E59FF018
E59FF018
E59FF018
E59FF018
E320F000
E59FF014
E59FF014
3C
E38
E54
E94
E78
DF0
E28
E59F026C
E59F126C
E5801000
E3A00000
E3A01000

r5_1_tcm_b:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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Observer
Observer
1,602 Views
Registered: ‎10-06-2018

I found that bit 0 of RPU1_CFG , addr 0xff9a0200, is cleared which means that the CPU is halted.

I am able to start r5_1 by setting this bit.

Therefore, a workaround is

a) load and start r5_1 with remoteproc

b) load and start r5_0 with remoteproc

r5_0 sets the bit 0 of RPU1_CFG to start r5_1.

Question remaining is why is it not done by remoteproc ?

View solution in original post

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