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Time Profiling of Xilinx OpenAMP IPC library[zynq ultrascale+ mpsoc]

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Adventurer
Posts: 74
Registered: ‎11-27-2010

Time Profiling of Xilinx OpenAMP IPC library[zynq ultrascale+ mpsoc]

[ Edited ]

Hi,

   1. Is there any time profiling done on the zynq Ultrascale mpsoc openAMP infrastructure?. if so, can you please point?

   2. Delta time between APU core (n) send and APU core (n+1) receive ?

   3. Delta time between APU send and RPU receive and vice-versa ?

 

Thanks

 

Adventurer
Posts: 74
Registered: ‎11-27-2010

Re: Time Profiling of Xilinx OpenAMP IPC library[zynq ultrascale+ mpsoc]

Hi Xilinx Team,

                       Is there any update to this.

 

1. I haven't see Xilinx publishing anything on time profiling.

2. I have seen wiki link on AMP, However it does not tell what is behind the AMP based IPC

 as per the link

http://www.wiki.xilinx.com/Zynq+UltraScale+MPSoC+Base+TRD+2017.1+-+Design+Module+4

i see DDR is being used for this APU-RPU communication.

if not, let me know what is it being used as basis for AMP communication.

 

Thanks

Visitor
Posts: 5
Registered: ‎03-20-2017

Re: Time Profiling of Xilinx OpenAMP IPC library[zynq ultrascale+ mpsoc]

I saw one of the examples or wiki's, but can't remember where, use 2 timer IP blocks.  The sender starts the timer right before calling send and the receiver stops the timer right after.  The 2 timers are one for each direction.

 

The timing will also depend on the receiving mechanism.  The examples show polling and interrupt behaviors.