03-14-2017 06:40 AM - edited 03-14-2017 07:26 AM
1. Is there any time profiling done on the zynq Ultrascale mpsoc openAMP infrastructure?. if so, can you please point?
2. Delta time between APU core (n) send and APU core (n+1) receive ?
3. Delta time between APU send and RPU receive and vice-versa ?
12-14-2017 08:31 AM
Hi Xilinx Team,
Is there any update to this.
1. I haven't see Xilinx publishing anything on time profiling.
2. I have seen wiki link on AMP, However it does not tell what is behind the AMP based IPC
as per the link
i see DDR is being used for this APU-RPU communication.
if not, let me know what is it being used as basis for AMP communication.
01-04-2018 05:17 AM
I saw one of the examples or wiki's, but can't remember where, use 2 timer IP blocks. The sender starts the timer right before calling send and the receiver stops the timer right after. The 2 timers are one for each direction.
The timing will also depend on the receiving mechanism. The examples show polling and interrupt behaviors.