UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor sergej
Visitor
720 Views
Registered: ‎08-02-2018

ZCU102 - Configure shared memory to be non-cachable for APU running bare metal

I want to use a shared memory region in DRAM for communication between the RPU and the APU, Both are running bare metal. In my test application, the RPU writes and the APU reads the data. It works, but I need to invalidate the cache before reading. Now, I would like to make it work without invalidating the cache before reading.

 

How do I configure this shared memory region as non-cachable in the APU?

Tags (3)
0 Kudos
2 Replies
Visitor sergej
Visitor
639 Views
Registered: ‎08-02-2018

Re: ZCU102 - Configure shared memory to be non-cachable for APU running bare metal

I think I have managed to configure a memory region as "outer shareable / non cached" with:

 

 

#include "xil_mmu.h"
Xil_SetTlbAttributes(NORM_NONCACHE | OUTER_SHAREABLE);

 

This changes the memory attributes setting in the translation table from 0x705 to 0x601. Can someone point me to a document where the meaning of these magic numbers is defined? Where is the translation table format specified?

 

0 Kudos
Visitor sergej
Visitor
633 Views
Registered: ‎08-02-2018

Re: ZCU102 - Configure shared memory to be non-cachable for APU running bare metal

This has helped armv8_a_address translation_100940_0100_en.pdf.

 

 

 0x705 => 0 1 11 00 0 010 01
            ^ ^^ ^^ ^ ^^^ ^^
            |  |  | |   |  |
            |  |  | |   |  +-> descriptor type => Block entry (levels 1 and 2) ?
            |  |  | |   +----> Indx (index into the MAIR_ELn) => MAIR_ELn[2] => **Device-nGnRnE**
            |  |  | +--------> NS (security bit)
            |  |  +----------> AP (access permission) => EL0 No access, EL1/2/3 Read and write
            |  +-------------> SH (shareability) => **Inner Shareable**
            +----------------> AF (access flag) =>  This block entry has been used
            
 0x601 => 0 1 10 00 0 000 01
            ^ ^^ ^^ ^ ^^^ ^^
            |  |  | |   |  |
            |  |  | |   |  +-> descriptor type => Block entry (levels 1 and 2) ?
            |  |  | |   +----> Indx (index into the MAIR_ELn) => MAIR_ELn[0] => **Normal, Inner/Outer Non-Cacheable**
            |  |  | +--------> NS (security bit)
            |  |  +----------> AP (access permission) => EL0 No access, EL1/2/3 Read and write
            |  +-------------> SH (shareability) => **Outer Shareable**
            +----------------> AF (access flag) =>  This block entry has been used

 

MAIR_ELn is defined in standalone/boot.S

 

    /**********************************************
    * Set up memory attributes
    * This equates to:
    * 0 = b01000100 = Normal, Inner/Outer Non-Cacheable
    * 1 = b11111111 = Normal, Inner/Outer WB/WA/RA
    * 2 = b00000000 = Device-nGnRnE
    * 3 = b00000100 = Device-nGnRE
    * 4 = b10111011 = Normal, Inner/Outer WT/WA/RA
    **********************************************/
    ldr      x1, =0x000000BB0400FF44
    msr      MAIR_EL3, x1

 

Am I right? Please correct me if I am wrong.

0 Kudos