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Contributor
Contributor
399 Views
Registered: ‎10-16-2018

基于xc7k325t 用selectio ip核 生成iserdes实现7:1的LVDS视频接口接收

按图一所示ip核设置  clk输出时钟为什么是clk_div(7分频后的时钟)?

不应该是输出7倍频后的时钟么????

图片1.png
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Xilinx Employee
Xilinx Employee
364 Views
Registered: ‎03-14-2016

Re: 基于xc7k325t 用selectio ip核 生成iserdes实现7:1的LVDS视频接口接收

Hello,

Since you have a serialization factor of 7, the clk_div is 1/7 of your data clock.  The clk_div will be the same rate as your received clock.  The PLL/MMCM will be used to generate a bit clock (Rx_clk * 7) and a pixel clock (Rx_clk).  This is explained in XAPP585.

Thank you

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