UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Observer aniket
Observer
1,284 Views
Registered: ‎09-26-2017

1 GHz or 800MHz with help PLL or CLK free counter work possible?

hello everyone,

 

 

 

I am working with the Spartan-6 sp605 board and there I have created a counter with 1Ghz or 800MHz clock or PLL  with working or not? please, specific answer replies me.

 

thanks 

0 Kudos
3 Replies
Observer avt_agui
Observer
1,265 Views
Registered: ‎07-07-2015

Re: 1 GHz or 800MHz with help PLL or CLK free counter work possible?

Datasheet P56 I think that it is impossible to see the specifications of FMAX in Table 48.
https://japan.xilinx.com/support/documentation/data_sheets/ds162.pdf

Mentor jmcclusk
Mentor
1,220 Views
Registered: ‎02-24-2014

Re: 1 GHz or 800MHz with help PLL or CLK free counter work possible?

If you are trying to measure an external clock of 800 or 1 GHz,  you might be able to do that by bringing it directly into a flip-flop clock input, and dividing it by 2.   But it's certainly true that you can't run a global clock tree at 800 Mhz..   400 MHz is the limit for Spartan6.

 

Don't forget to close a thread when possible by accepting a post as a solution.
0 Kudos
Xilinx Employee
Xilinx Employee
1,101 Views
Registered: ‎06-30-2010

Re: 1 GHz or 800MHz with help PLL or CLK free counter work possible?

@aniket as @avt_agui has explained the Fmax for the BUFG in Spartan-6 is 400Mhz - Table 48 page 56 of the DS above. you cannot hit that 1 Ghz speed. The ISERDES can sample @ 800Mbps using the BIFG or @ 1080Mbps using the BUFPLL and doing a Double Data rate. But that is just sampling and not a counter.
If you want a counter and so the FPGA fabric running at these speeds then the limitation is the Fmax of the BUFG.
-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos