cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Newbie
Newbie
4,540 Views
Registered: ‎08-10-2015

100Mhz Clock Pinout (Nexys4)

Hi all,

 

I do generate 100Mhz and 10Mhz clock signal using Clocking Wizard IP

 

and I try to signal out through MRCC GPIO Pin.

 

I measured two clock signal by oscilloscope,

 

10Mhz clock signal is ok but 100Mhz clock signal is not measured(zero Signal).

 

Is there hardware out frequency limit??

 

Thanks for reading my message^^

 

 

This is very simple VHDL Code.^^

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity main is
Port ( clock_in : in STD_LOGIC;
reset_in : in STD_LOGIC;
clock_10M : out STD_LOGIC;
clock_100M : out STD_LOGIC);
end main;

architecture Behavioral of main is

signal clock_locked : std_logic := '0';

component clk_gen
port
(-- Clock in ports
clk_in : in std_logic;
-- Clock out ports
clk_100M : out std_logic;
clk_10M : out std_logic;
-- Status and control signals
reset : in std_logic;
locked : out std_logic
);

end component;

begin

amd_clk : clk_gen
port map (

-- Clock in ports
clk_in => clock_in,
-- Clock out ports
clk_100M => clock_100M,
clk_10M => clock_10M,
-- Status and control signals
reset => reset_in,
locked => clock_locked
);

end Behavioral;

0 Kudos
3 Replies
Highlighted
Moderator
Moderator
4,528 Views
Registered: ‎01-15-2008

check the following link for the datasheet of artix-7 fpga which provides you the mmcm specs

http://www.xilinx.com/support/documentation/data_sheets/ds181_Artix_7_Data_Sheet.pdf

 

I believe you are referring to this board 

https://www.digilentinc.com/Data/Products/NEXYS4/Nexys4_RM_VB2_Final_5.pdf

 

could you share your xci file of the clocking wizard to check the settings

Highlighted
Newbie
Newbie
4,471 Views
Registered: ‎08-10-2015

Thanks for reply. :)

 

It was All My mistake.

 

I'm a beginner of FPGA.

 

I really appreciate your reply.

0 Kudos
Highlighted
Scholar
Scholar
4,441 Views
Registered: ‎06-05-2013

@nickby Is the issue solved?

-Pratham

----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
0 Kudos