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Registered: ‎06-14-2018

16-bit DAC sigma-delta IP for Artiy-7

I need to output 8 analog channels to an Arty-7 board. All signals must be available simultaneously (I cannot multiplex them using a single DAC output channel).

  1. 1MHz Sine wave
  2. 25MHz Sine wave
  3. 50MHz Sine wave
  4. 10kHz to 100kHz Sine sweep signal
  5. 1MHz to 10MHz Sine sweep Signal
  6. 10MHz and 10kHz superimposed sine waves
  7. 500kHz sine wave with 2ns glitches superimposed. The glitch occurs about every 90us with variable position.
  8. 250kHz sine wave with 25MHz superimposed sine wave

I know how to produce the 16-bit wide signals required for each one of these channels usind DDS Compiler IPs, but I need to find a cost effective way to convert these outputs to analog so that I reduce the pin count. I thought about using 16-bit sigma-delta DAC, but I could not find suitable IP cores for the 7 Series FPGAs.

In fact, I could not find 16-bit sigma-delta DAC at all.

I would like to get some information on how to implement this without using external DACs so that cost and pin-count is reduced.

Can anybody point me to an existing 16-bit Sigma-Delta DAC IP core for the 7 Series FPGA?


Many thanks,



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3 Replies
Registered: ‎01-08-2012

Re: 16-bit DAC sigma-delta IP for Artiy-7

It sounds like you want to produce a 16 bit accurate, 50MHz sinusoid using a 1 bit DAC.  Did you calculate the oversampling rate required to do that?  (I didn't, but) I suspect it's higher than the maximum toggle rate of the SelectIO.

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Registered: ‎06-14-2018

Re: 16-bit DAC sigma-delta IP for Artiy-7

Good point. I will need external DAC for the higher frequencies. But I still need the sigma-delta for the lower frequencies.

Any idea on available IPs?

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Registered: ‎01-08-2012

Re: 16-bit DAC sigma-delta IP for Artiy-7

    I will need external DAC for the higher frequencies.

Not necessarily.  For example, if the 50MHz signal was just a fixed 50MHz (and never needed to be anything other than 50MHz) you could simply output a 50MHz square wave on an IO pin and filter out the harmonics using an RC or RLC circuit.  That's really simple to do, assuming you don't have stringent harmonic requirements.

Similarly, the 2ns glitch could just be a logic signal from an ODDR clocked from 250MHz (or an output FF clocked from 500MHz, but stick with the 250MHz option - it's easier to deal with).

The swept frequencies can probably be handled by a DSM DAC.  You will need a analog low pass filter on the output.

Another thing I should mention is that you are relying on the analog voltages at an FPGA output.  These outputs are fine for driving logic, but do not expect 16 bits of analog accuracy.

    Any idea on available IPs?

No, but the last time I put a delta sigma modulator inside an FPGA, I wrote and tested it myself in an afternoon.  It's not that hard.  The core code that does the heavy lifting is only one or two lines of VHDL or Verilog, IIRC.

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