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Visitor gumersindo
Visitor
925 Views
Registered: ‎10-22-2018

50 MHz clock to output pin oscilloscope

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Hello everybody!

 

I am still very new.

 

I want to see a 50 MHz clock as perfect as possible in the oscilloscope, just to check that it meets some timing requirements (like rising/falling time...).

 

I have a Zybo board and I am using Vivado. My first idea was to simply forward one of the "PL Fabric Clocks" (available in the "Zynq Processing System" IP) to an output PMOD pin. But, as I have seen in other posts, it is not working nicely (even using Hi-Speed PMOD pins). I tried also changing the pin parameters "Drive Strenght" and "Slew Type", but I did not notice change at all.

 

I have also read about using ODDR (Clock Forwarding) but I still do not understand how to add that IP to my block design (I can add oddr from the IP Catalog, but I cannot configure anything).

 

I am also afraid that impedance mismatching is probably affecting. I am using an agilent 10:1 probe and in the oscilloscope I have to select 1Mohm impedance for the channel I am using (other case I cannot see anything). The oscilloscope is MSO6104 from Agilent (has enough bandwidth).

 

Could you guide me a little bit?

 

Thanks in advance,

 

Kind regards,

 

Gumersindo

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Moderator
Moderator
912 Views
Registered: ‎08-08-2017

Re: 50 MHz clock to output pin oscilloscope

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Hi @gumersindo

 

You must be getting  this when adding the ODDR in the IPI.

Capture.PNG

in the back end RTL of this IP,  D1 and D2 inputs are connected to Logic '1' and Logic '0' such that , the output of the ODDR will generate a high at posedge of the clock and a low at negedge of the clock]

 

Capture1.PNG

 

 

So you dont need to configure anything here, just connect the clkin input to the clock you want to forward , make clkout external and route it to any GPIO.

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Reply if you have any queries, give Kudos and Accepts as solution

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Reply if you have any queries, give kudos and accept as solution
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5 Replies
Moderator
Moderator
913 Views
Registered: ‎08-08-2017

Re: 50 MHz clock to output pin oscilloscope

Jump to solution

Hi @gumersindo

 

You must be getting  this when adding the ODDR in the IPI.

Capture.PNG

in the back end RTL of this IP,  D1 and D2 inputs are connected to Logic '1' and Logic '0' such that , the output of the ODDR will generate a high at posedge of the clock and a low at negedge of the clock]

 

Capture1.PNG

 

 

So you dont need to configure anything here, just connect the clkin input to the clock you want to forward , make clkout external and route it to any GPIO.

-----------------------------------------------------------------------------------------------------------------

Reply if you have any queries, give Kudos and Accepts as solution

----------------------------------------------------------------------------------------------------------------

 

-------------------------------------------------------------------------------------------------------------------------------
Reply if you have any queries, give kudos and accept as solution
-------------------------------------------------------------------------------------------------------------------------------
Visitor gumersindo
Visitor
898 Views
Registered: ‎10-22-2018

Re: 50 MHz clock to output pin oscilloscope

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Hi @pthakare,

 

First of all, thank you so much for your reply!

 

Yes, that is exactly what it looks like now, and as you just said everything is by default OK for what I need.

 

But still I see this (image1) on the oscilloscope (using pin V12 of PMOD JE). I am expecting a more squared waveform (aiming for 2 ns of rising/falling time) and I see also that the amplitud is not 3.3V.

 

My workflow is:

 

Block desing as you see (image2), generate output products, create HDL wrapper, synthesis (and I select the pin and rest of parameters as you also see, image3), implementation, generate bitstream, export hardware --> then I launch SDK, program FPGA and run a simple app with a "while(1)" loop.

 

Is there something I am missing (in the workflow or impedance mismatching)? Or how do I improve the waveform?

 

Thanks,

 

Gumersindo

image1.PNG
image2.PNG
image3.PNG
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Moderator
Moderator
861 Views
Registered: ‎04-18-2011

Re: 50 MHz clock to output pin oscilloscope

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The problem here is not the FPGA ODDR. 

I think you should try to understand there is always some capacitive load on it when you measure it. 

 

The scope and indeed the scope probe will load the output. It depends if you are using the correct probe or not. 

The fact that you say it only works when the coupling is set to 1Mohm points to the probe somehow. 

 

Keith 

 

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833 Views
Registered: ‎06-21-2017

Re: 50 MHz clock to output pin oscilloscope

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The Zybo schematic https://reference.digilentinc.com/learn/documentation/schematics/zybo-schematic shows 200 ohm resistors in series with the signal and clamping diodes on the pins.  This will form a low pass filter, but I wouldn't expect the capacitance of the diodes would be enough to round the signal this much.  Your scope probe is grounded?  Are you looking right on the PMOD pin or over a cable?

Visitor gumersindo
Visitor
821 Views
Registered: ‎10-22-2018

Re: 50 MHz clock to output pin oscilloscope

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Hi @bruce_karaffa,

 

Yes, I think the same.

 

The scope probe I am using right now is 10073C from Agilent. And it is grounded with the alligator to one of the GND pins from the PMOD (or simply touching the metallic part of the USB or HDM connector, for example). On the other hand, I am looking right on the PMOD pin, although I also tried over a cable using the retractable hook tip, but the result was a little worse.

 

I am trying to figure out what is the problem using the info in these two links (and some other pdfs):

 

https://www.radio-electronics.com/info/t_and_m/oscilloscope/oscilloscope-probes.php

http://www.ni.com/white-paper/14825/en/                 (figure 9)

 

And I am making an scheme (see attached image) like the ones in the links, but there is still something I am missing or confusing.

 

 

Any help is welcome,

 

Thanks a lot

img1.jpg
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