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rakend_r
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7 Series GTX QPLL doubts

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Hi,

 

I've generated GTX example design using gt_wizard. By looking at the codes, I'm having some doubts regarding QPLL configuration.

 

 qpll.PNG

 

 

Following is the doubt:

Input GT reference clk to QPLL is 125MHz. N (QPLL_FBDIV) is 40, M (QPLL_REFCLK_DIV) is 1. So according to this PLL out clock is 2.5GHz. So what is the VCO frequency? If this is twice the output frequency, it will be 5MHz. But why this is not specified in the operating range?

 

 

 

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ashishd
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Hello @rakend_r,

 

I generated example design with these parameters for GTX transceivers and observed below values for QPLL attributes -

 

QPLL_REFCLK_DIV (M) = 1

QPLL_FBDIV/QPLL_FBDIV_RATIO (N) = 80

TX/RXOUT_DIV (D) = 4

 

So the calculations considering these values are 

 

PLL output frequency = 125 * (80 / 2) = 5000 MHz

 

Wherein VCO frequency is 125 * 80 = 10 GHz . So in this case upper band frequency is used for VCO.

You can cross-verify this by checking 6th bit of QPLL_CFG attribute. It is 0 when upper band is used.

 

In general, according to your selection of line rate and PLL (CPLL/QPLL), divider value (TX/RXOUT_DIV) is appropriately chosen by the wizard (as per the datasheet of device selected) and then remaining values are so adjusted to have VCO frequency in either of the bands.

 

Hope this clears the confusion.

Regards,
Ashish
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balkris
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check this one related ARs it may help you partially
http://www.xilinx.com/support/answers/43244.html
Thanks and Regards
Balkrishan
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rakend_r
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Hi,

 

I'm trying to understand what they are given in the datasheet. With my settings, what is the VCO frequency and in which band it falls?

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balkris
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see ARs foot note it mention

For QPLL operating in 5.93 GHz to 6.6 GHz range which is  VCO frequency

 

 

Thanks and Regards
Balkrishan
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rakend_r
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Hi, I didn't get the answer from that AR. Question is that the GT example design gives some parameters, N = 80 , M = 1. My input clock is 125MHz. So the Output clk will be 2.5GHz, which leads to 5GHz VCO frequency (Is this correct?), if so, nominal operating range as per datasheet starts from 5.93 GHz. So what I'm missing here.
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balkris
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sure no issue . You must have to set the M and N value such that the VCO frequency in the given range of PLL.

 

This is my understanding let me check again

Thanks and Regards
Balkrishan
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rakend_r
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FYI ,

 

 

Aurora 8B10B Example design gives QPLL configuration as N = 40 , M = 1 for 125MHz, which leads to VCO frequency of 5GHz. This is NOT in the operating range of VCO frequency as per Kintex7 DC and Switching Characteristics Datasheet.

 

But in the GTXE2_CHANNEL is configured to select CPLL instead of QPLL. So the above configuration is of no use at all..

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balkris
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@venkata

Adding venkata if he can comment for Aurora core
Thanks and Regards
Balkrishan
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venkata
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Aurora 8B10B does not use QPLL.

QPLL is instantiated in the IP only to ensure bias_cfg parameter is set properly as per the AR below.
http://www.xilinx.com/support/answers/43339.html

The IP may not configure the QPLL for the target line rate since it is not used in the design.
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ashishd
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Hello @rakend_r,

 

Can you tell us the line rate selected by you while customizing wizard?

Regards,
Ashish
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rakend_r
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2.5Gbps with 125MHz ref clock.

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ashishd
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Registered: ‎02-14-2014

Hello @rakend_r,

 

I generated example design with these parameters for GTX transceivers and observed below values for QPLL attributes -

 

QPLL_REFCLK_DIV (M) = 1

QPLL_FBDIV/QPLL_FBDIV_RATIO (N) = 80

TX/RXOUT_DIV (D) = 4

 

So the calculations considering these values are 

 

PLL output frequency = 125 * (80 / 2) = 5000 MHz

 

Wherein VCO frequency is 125 * 80 = 10 GHz . So in this case upper band frequency is used for VCO.

You can cross-verify this by checking 6th bit of QPLL_CFG attribute. It is 0 when upper band is used.

 

In general, according to your selection of line rate and PLL (CPLL/QPLL), divider value (TX/RXOUT_DIV) is appropriately chosen by the wizard (as per the datasheet of device selected) and then remaining values are so adjusted to have VCO frequency in either of the bands.

 

Hope this clears the confusion.

Regards,
Ashish
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rakend_r
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Thanks @ashishd

Can you check the same using Aurora 8B10B example design?
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ashishd
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Hello @rakend_r,

 

In Aurora 8B10B example design, QPLL is only instantiated to have BIAS_CFG parameter set properly. It uses channel PLL to achieve desired line rate. You can cross-check it by verifyingTXSYSCLKSEL[1:0] port of GTXE2_CHANNEL.

You will find that both these bits are tied to ground which means CPLL output clock if forwarded to TX datapath and TXOUTCLK generation logic. 

So in this case, you need to look in for CPLL calculations which are mentioned on page #47 in below UG

http://www.xilinx.com/support/documentation/user_guides/ug476_7Series_Transceivers.pdf

 

Regards,
Ashish
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rakend_r
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I've confirmed that Aurora is using CPLL by checking SYSCLKSEL. But I was wondering why it has instantiated QPLL. I'm unaware about the usage of BIAS_CFG.

I've a design which is created from Aurora example design which uses CPLL. I wanted to change that to QPLL. And I found that the QPLL is instantiated with wrong configuration and CPLL is used. All confusion started from this.

Thanks a lot for clearing it.

PS : Where can I find the doc for BIAS_CFG ? In UG, it is saying reserved use. And How can i convert the Aurora Example design from CPLL to QPLL?
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ashishd
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Hello @rakend_r,

 

Please check below AR to know details about BIAS_CFG

http://www.xilinx.com/support/answers/43339.html

 

May I know the purpose behind switching CPLL to QPLL? Because if we take an example of KC705 board device xc7k325tffg900-2, maximum line rate supported is 6.6 Gbps for Aurora 8B10B and as per datasheet CPLL supports maximum line rate of 6.6 Gbps.

Regards,
Ashish
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rakend_r
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I'm referring to Aurora 8B10B example to design my code with 3 lanes. Each is of 2.5Gbps. I've been advised to use QPLL instead of CPLL in that design. Protocol is custom.
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rakend_r
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Hi @ashishd,

Just one doubt.

As per your reply, QPLL is required even if we are using only CPLL. Is there any documentation regarding this?
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